Two-Stage Memory Programming Reduces Verify Loops

Solution Overview

Problem

Current non-volatile memory apparatuses face challenges in efficiently programming memory cells due to the time-consuming nature of verify tests, which increase as the number of data states grows, leading to degraded performance and wider threshold voltage distributions.

Innovation Solution

A two-stage programming approach is implemented, where the first programming stage ends before all memory cells are verified, leaving a fraction below the verify voltage, and a second stage ensures a predetermined number of cells meet the verify voltage, reducing the number of verify loops and improving programming efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If verify tests are performed for all memory cells in a single programming stage, then programming accuracy is improved, but program time increases and performance degrades

Engineering Contradiction:

Improveprogramming accuracyVSAvoidprogram time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The programming operation is divided into two distinct stages: a first programming stage that programs memory cells to intermediate program states, and a second programming stage that programs memory cells to final program states. This segmentation allows the verify test to be performed at an intermediate point, reducing the total number of verify loops required while maintaining programming accuracy through the two-stage approach.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If the number of data states increases, then storage capacity is improved, but verify test time increases and performance degrades

Engineering Contradiction:

Improvestorage capacityVSAvoidperformance

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The programming operation is divided into two distinct stages: a first programming stage that programs memory cells to intermediate program states, and a second programming stage that programs memory cells to final program states. This segmentation allows the verify test to be performed at an intermediate point, reducing the total number of verify loops required while maintaining programming accuracy through the two-stage approach.

Inventive Principle:

Principle #1Segmentation

3Reliability

If all memory cells are verified in the first programming stage, then programming reliability is improved, but the number of verify loops increases and efficiency decreases

Engineering Contradiction:

Improveprogramming reliabilityVSAvoidprogramming efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The first programming stage performs a partial verify test that does not verify all memory cells to completion. Instead, it verifies memory cells to an intermediate state, leaving a fraction of memory cells below the verify voltage. This partial action reduces the number of verify loops required while maintaining sufficient reliability through the subsequent second programming stage.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The programming operation is divided into two distinct stages: a first programming stage that programs memory cells to intermediate program states, and a second programming stage that programs memory cells to final program states. This segmentation allows the verify test to be performed at an intermediate point, reducing the total number of verify loops required while maintaining programming accuracy through the two-stage approach.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11244734B2Modified verify scheme for programming a memory apparatus

Publication Date: 2022.02.08 SANDISK TECHNOLOGIES LLC

AI summary

A memory apparatus and method of operation is provided. The apparatus includes memory cells coupled to a control circuit. The control circuit is configured to perform a first programming stage including iteratively programming each of the memory cells to first program states and verifying that the memory cells have a threshold voltage above one of a plurality of first verify voltages corresponding to the first program states. The first programming stage ends before all of the memory cells are verified thereby leaving a fraction of the memory cells below the one of the plurality of first verify voltages. The control circuit also performs a second programming stage including iteratively programming each of the memory cells to second program states and verifying that at least a predetermined number of the memory cells have the threshold voltage above one of a plurality of second verify voltages corresponding to the second program states.