Semiconductor Memory Device Programming Voltage Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving accurate programming of memory cells due to variations in cell characteristics, leading to inconsistent program voltages and prolonged programming times.
Innovation Solution
The method involves classifying memory cells into fast, typical, and slow categories based on initial programming and verification voltages, and applying sequentially increasing word line program voltages and decreasing bit line program voltages to optimize programming efficiency, ensuring each cell type receives appropriate voltage levels for precise programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If uniform program voltages are applied to all memory cells, then the programming process is simple, but program accuracy deteriorates due to cell characteristic variations
Solution Approach 1:
The patent applies different bit line program voltages to different memory cell groups based on their programming characteristics. Fast cells receive first bit line program voltage, typical cells receive second bit line program voltage, and slow cells receive third bit line program voltage. This local differentiation of voltage levels resolves the contradiction by enabling accurate programming of each cell type without requiring complex individual cell control.
Solution Approach 2:
The patent segments memory cells into three distinct groups (fast cells, typical cells, and slow cells) based on their programming characteristics. This segmentation allows the application of differentiated voltage levels to each group, achieving high program accuracy while maintaining relatively simple control logic through group-based voltage assignment.
2Manufacturing precision
If adaptive voltage adjustment is implemented for each memory cell, then program accuracy improves, but device complexity increases
Solution Approach 1:
Instead of implementing complex individual cell control, the patent applies local quality by assigning different voltage levels to different cell groups. The control logic remains relatively simple while achieving accurate programming through group-based voltage differentiation based on cell programming speed characteristics.
Solution Approach 2:
The patent dynamically adjusts bit line program voltages based on cell classification during the programming process. The voltage generator provides different voltages (first, second, or third bit line program voltages) to different bit lines depending on the classified status of connected memory cells, enabling adaptive control without requiring complex real-time individual cell monitoring.
3Manufacturing precision
If sequential voltage application is used for all cell types, then programming time increases, but program accuracy improves
Solution Approach 1:
The patent segments the programming process into parallel operations for different cell groups. Fast cells, typical cells, and slow cells receive different bit line program voltages simultaneously during the same programming operation, allowing parallel progress across cell groups while maintaining accuracy through differentiated voltage levels.
Solution Approach 2:
The patent employs dynamic voltage adjustment where the voltage generator adaptively provides appropriate bit line program voltages to different bit lines based on cell classification. This enables optimized programming timing for each cell type without requiring sequential processing, reducing overall programming time while maintaining high accuracy.
Data Source
AI summary
A semiconductor memory device and a method of programming the same are provided which can improve the program accuracy by classifying cells depending on a program status of memory cells during a program operation to control a bit line program voltage. The method comprises classifying memory cells to be programmed based on program characteristics of the memory cells and sequentially providing word line program voltages having increasing voltage levels and bit line program voltages having decreasing voltage levels to the classified memory cells in a program operation, wherein differently classified two memory cells receive different bit line program voltages, respectively.