Memory Programming Method Reducing Threshold Voltage Distribution Width
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Solution Overview
Problem
Multi-level cell (MLC) memory devices face increased read-failure rates due to overlapping threshold voltage distributions as the number of bits stored in a single memory cell increases, leading to reliability issues and errors during data reading.
Innovation Solution
A memory device and method that apply a series of pulses with incrementing program voltages to memory cells, using a programming unit to adjust the threshold voltage within specific ranges and a control unit to determine voltage increments, thereby reducing the width of threshold voltage distributions and minimizing errors during data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in a single memory cell increases, then the storage capacity is improved, but the read-failure rate increases due to overlapping threshold voltage distributions
Solution Approach 1:
The patent segments the programming process into multiple distinct phases: a first programming phase that programs memory cells to a first threshold voltage level, and a second programming phase that programs memory cells to a second threshold voltage level. This segmentation allows independent optimization of each programming phase, reducing the overlap between threshold voltage distributions for different data states while maintaining high storage capacity in MLC memory cells.
2Productivity
If the number of bits programmed in a single memory cell increases, then the integration density is improved, but the threshold voltage distributions overlap leading to increased read-failure rate
Solution Approach 1:
The patent employs dynamic programming voltages and time intervals for different programming phases. The first programming phase uses a first programming voltage and first time interval, while the second programming phase uses a second programming voltage and second time interval. This dynamic approach allows precise control over threshold voltage distribution width and separation, enabling higher integration density with reduced read-failure rates by adapting programming parameters to the specific requirements of each data state.
3Device complexity
If the same programming voltage is applied to all memory cells, then the programming process is simplified, but the threshold voltage distribution width increases reducing reliability
Solution Approach 1:
The patent applies different programming voltages and time intervals to different groups of memory cells based on their target threshold voltage levels. The first programming phase applies a first programming voltage to program memory cells to a first threshold voltage, while the second programming phase applies a second programming voltage to program memory cells to a second threshold voltage. This localized programming approach reduces the width of threshold voltage distributions for each data state, improving reliability while maintaining manageable process complexity through systematic voltage application.
Data Source
AI summary
Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.