Multi-Page Memory Programming to Reduce Word-Line Interference
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The decreasing spacing between word lines in memory devices leads to electrical interference, degrading data reliability and causing a programming bottleneck due to the need to slow down programming speed to mitigate interference.
Innovation Solution
A memory device with a control logic that controls the peripheral circuit to program data distributively across multiple pages based on the stage of the program operation, using methods like TLC, MLC, and SLC, thereby reducing electrical interference without altering signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between word lines is decreased to increase storage capacity, then the storage density is improved, but electrical interference between adjacent word lines increases degrading data reliability
Solution Approach 1:
The patent segments the programming operation into multiple stages, dividing the data to be programmed into multiple pages. Instead of programming all data to a single page sequentially, the control logic distributes different portions of the data across multiple pages (e.g., first page data, second page data, third page data) and programs them in an interleaved manner. This segmentation reduces the concentration of electrical signals on adjacent word lines at any given time, thereby reducing interference while maintaining high storage utilization.
Solution Approach 2:
The patent applies preliminary action by receiving and buffering multiple pages of data before completing the programming operation. The control logic receives all necessary page data in advance, then strategically programs them across different pages in a predetermined sequence. This allows the system to prepare the data distribution plan beforehand, ensuring that interference is minimized during the actual programming phase while maintaining data reliability.
2Reliability
If the transmission of programming signals is alternated over adjacent word lines to reduce interference, then data reliability is improved, but programming speed decreases causing a programming bottleneck
Solution Approach 1:
The patent segments both the data and the target pages, dividing the programming task into multiple parallel streams. Instead of alternating signals sequentially on adjacent word lines, the system simultaneously programs different segments of data to different pages using different word lines. This parallel segmentation maintains data reliability by distributing signals while avoiding the speed penalty of sequential alternation.
Solution Approach 2:
The patent transitions from a one-dimensional sequential alternation approach to a multi-dimensional parallel programming approach. By introducing the dimension of multiple pages and distributing data across them, the system can program multiple word lines simultaneously rather than alternating them sequentially. This dimensional expansion allows the system to maintain high programming speed while reducing interference through spatial distribution of signals.
3Device complexity
If the programming operation is performed on a single page at a time, then the programming logic is simple, but the programming speed is limited due to sequential processing
Solution Approach 1:
The patent segments the data into multiple pages and the programming operation into multiple stages, allowing parallel processing of different page segments. The control logic manages these segmented operations through systematic control signals, maintaining reasonable complexity while achieving higher throughput through parallel execution of programming tasks on different pages.
Solution Approach 2:
The patent makes the programming system multi-functional by enabling it to simultaneously program multiple pages with different data segments using a unified control framework. The control logic serves multiple functions: receiving data, determining page distribution, generating control signals for different word lines, and coordinating the parallel programming operations. This universality allows the system to maintain relatively simple overall architecture while achieving high programming speed through parallel multi-page operations.
Data Source
AI summary
A memory device includes a memory cell array including a plurality of pages; a peripheral circuit for performing a program operation; and a control logic for controlling the peripheral circuit to, when a program command for a first page among the plurality of pages and a plurality of page data are received, program a second page based on one page data among the plurality of page data, and program the first page based on other page data, according to a stage of the program operation.