3D Memory Current Pulse Profiling for Faster Writes and Lower Read Disturb
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Solution Overview
Problem
Existing memory operations in 3D memory architectures face long latency times (>125 ns) or high set threshold voltages due to the use of square current pulses, which either prolong programming time or lead to selector devices getting stuck at high voltages, resulting in suboptimal memory window performance.
Innovation Solution
Applying a current pulse close to the melt current of the selector material, followed by a step-down or ramp-down regime to reduce current levels, interrupting nucleation processes and oscillating nuclei sizes for improved write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a square current pulse at a specified single current level (30-60 uA) is used for set and read setback operations, then the current level is controlled, but the programming time becomes very long (>125 ns) to achieve a desired memory window (>300 mV)
Solution Approach 1:
The patent applies a dynamic current pulse profile instead of a static square pulse. The current level transitions from an initial high level (60-90 uA) to a final low level (20-40 uA) through a controlled reduction phase, creating a time-varying current profile that optimizes both programming speed and memory window achievement
Solution Approach 2:
The patent changes the current parameter dynamically during the programming operation. By varying the current level over time (high initial current for rapid nucleation, then reduced current for controlled growth), the system achieves faster programming times while maintaining the desired memory window, resolving the contradiction between current control and programming time
2Productivity
If a high current level (60-90 uA) is applied to reduce programming time, then the speed increases, but the selector device remains stuck at a relatively high set threshold voltage with reduced memory window
Solution Approach 1:
The patent employs a multi-phase current pulse sequence: an initial high-current phase for rapid nucleation, followed by a reduction phase to lower current levels. This periodic variation in current application allows the system to achieve fast initial programming while subsequent current reduction ensures proper threshold voltage setting and memory window formation
Solution Approach 2:
The patent uses a high initial current level to rapidly nucleate the phase change material, skipping the slow initial formation phase. This rush-through approach achieves rapid programming initiation, while the subsequent current reduction phase ensures the selector device settles at the correct threshold voltage, preventing it from getting stuck at high voltage states
3Loss of energy
If a low current level (30 uA) is used for read operations, then the power consumption is reduced, but the read disturb bit error rate increases in multi-level cell applications
Solution Approach 1:
The patent applies a preliminary high-current pulse before the actual read operation to reset or prepare the selector device state. This preliminary action ensures the selector is in a known state, preventing read disturb errors that would otherwise occur with low-current read operations in MLC applications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces write and read latency by 1.5 to 2 times, increases memory window by 15% to 25%, and significantly reduces read disturb bit error rates in multi-level cell applications.
Implementation Method 1
Applying a current pulse close to the melt current of the selector material
Implementation Method 2
current pulse close to the melt current of the selector material, followed by a step-down or ramp-down regime
Data Source
AI summary
A method, apparatus and system. The apparatus includes one or more processors to: determine that a memory operation including one of a write operation or a read operation is to be implemented on a memory cell of a memory array, the memory operation having a duration equal to a latency window and being based on a voltage change across the memory cell equal to a target memory window; and in response to a determination that the memory operation is to be implemented, cause, during the latency window, an application of a current pulse amplitude profile to the memory cell, wherein the current pulse amplitude profile decreases progressively, encompassing at least four different current pulse amplitudes, the at least four different current pulse amplitudes including a highest current pulse amplitude and a lowest current pulse amplitude.