Memory Pump Clock Scaling by Active Block Count
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Solution Overview
Problem
Flash memory devices consume excessive current in peripheral circuits due to fixed clock frequencies set for the maximum number of activated memory blocks, even when fewer blocks are active, leading to unnecessary power consumption.
Innovation Solution
A memory device with a voltage generator and control logic that adjusts clock frequency based on the number of active blocks, allowing independent memory operations and reducing current consumption in peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is set considering the maximum number of memory blocks that are activated simultaneously, then the memory device can handle maximum parallel operations, but excessive current is consumed unnecessarily when fewer blocks are activated
Solution Approach 1:
The patent implements dynamic clock frequency adjustment in the pump circuit based on the number of actively selected memory blocks. The control logic dynamically changes the clock frequency according to the actual operation demand, allowing the system to maintain high productivity when maximum blocks are activated while reducing current consumption when fewer blocks are active. This dynamic adaptation resolves the contradiction between maintaining peak performance capability and minimizing actual energy usage.
Solution Approach 2:
The patent changes the clock frequency parameter of the pump circuit based on the number of activated memory blocks. When fewer blocks are selected, the clock frequency is reduced accordingly, which directly reduces the current consumption in the peripheral circuit while still maintaining the capability to operate at maximum frequency when all blocks are activated. This parameter adjustment strategy effectively balances productivity and energy efficiency.
2Device complexity
If a fixed clock frequency is used for generating operating voltage, then the circuit design is simplified, but current consumption increases when the number of active blocks is less than maximum
Solution Approach 1:
The patent introduces dynamic clock frequency control in the pump circuit while maintaining relatively simple circuit architecture. The control logic adjusts the clock frequency based on the number of actively selected memory blocks, enabling the system to reduce current consumption during partial activation without requiring complex circuit redesign. This approach achieves energy efficiency with minimal increase in device complexity.
3Use of energy by moving object
If the clock frequency is reduced to lower current consumption, then power efficiency improves, but the memory device cannot handle maximum parallel operations
Solution Approach 1:
The patent implements dynamic clock frequency adjustment that allows the memory device to operate at reduced frequencies for power efficiency during normal operations, while maintaining the capability to switch to maximum frequency when all memory blocks are activated simultaneously. This ensures both power efficiency under typical conditions and full productivity capability when needed, resolving the contradiction between the two requirements.
Solution Approach 2:
The patent changes the clock frequency parameter dynamically based on the number of activated memory blocks. The system can operate at lower frequencies to improve power efficiency when fewer blocks are active, while retaining the ability to increase frequency to maximum levels when all blocks are activated, thus maintaining full parallel operations capability when required.
Data Source
AI summary
A memory device is disclosed including a memory cell array, a voltage generator, and a control logic. The memory cell array has a plurality of active blocks, each active block including a plurality of memory cells operating at the same clock frequency. The voltage generator provides an operating voltage to the plurality of memory cells. The control logic controls an independent memory operation for each active block. The voltage generator includes a pump circuit which changes a clock frequency for generating the operating voltage according to a number of active blocks activated during the independent memory operation.