Memory Rank Delay Tuning via Nonvolatile Storage
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Solution Overview
Problem
As memory systems become increasingly complex, there is a need for new techniques to effectively control the timing and access operations of multiple memory chips in a memory rank, which is not efficiently addressed by existing technologies.
Innovation Solution
A memory device with at least two memory ranks sharing input/output lines, a mode register to store bits for tuning delays of data signals, and a controller to determine tuning parameters, including delays, which are stored in a nonvolatile memory to optimize data signal alignment and electrical parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory chips are connected to the same chip select signal to form memory ranks for concurrent access, then memory capacity and access parallelism are improved, but timing control complexity and signal alignment difficulty increase
Solution Approach 1:
The patent applies preliminary action by performing delay tuning and calibration of data signals from multiple memory chips before they are put into normal operation. The system pre-adjusts the timing parameters of each chip in the memory rank during initialization, storing the calibrated values in mode registers. This preliminary calibration ensures that when multiple chips operate concurrently, their signals are already synchronized, eliminating the need for complex real-time timing control during data access operations.
2Speed
If delay tuning parameters are stored in volatile memory, then write access speed is fast, but the parameters are lost during power cycle requiring repeated tuning
Solution Approach 1:
The system performs delay tuning during manufacturing or initial setup and stores the calibrated parameters in nonvolatile memory (such as OTP or EEPROM). This preliminary calibration ensures that when the device is powered on, the tuned parameters are already available and do not need to be re-measured or re-adjusted, eliminating repeated tuning time during power-up cycles while maintaining fast access performance.
Solution Approach 2:
The patent implements copying by transferring the delay tuning parameters from nonvolatile memory (where they are permanently stored) to volatile memory (such as mode registers) during initialization. This copying mechanism allows the system to retain the benefits of nonvolatile storage (parameters persist across power cycles) while enabling fast read access during operation, as the parameters are quickly loaded into volatile memory at startup.
3Device complexity
If conventional tuning methods are used without nonvolatile memory, then device complexity is low, but tuning parameters cannot be retained across power cycles
Solution Approach 1:
The system performs delay tuning during manufacturing or initial setup and stores the calibrated parameters in nonvolatile memory (such as OTP or EEPROM). This preliminary calibration ensures that when the device is powered on, the tuned parameters are already available and do not need to be re-measured or re-adjusted, eliminating repeated tuning time during power-up cycles while maintaining fast access performance.
Data Source
AI summary
A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.