Memory Read Circuit High-Pass Filter Peak Hold
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistance change type memory devices, such as MRAM, face challenges in achieving high-speed read operations while minimizing read errors due to variations in resistance values and manufacturing variations, which affect the read margin and sense timing.
Innovation Solution
The implementation of a read circuit that includes a high-pass filter circuit and a peak hold circuit to extract and convert high-frequency components of the read signal into a DC signal, allowing for improved read accuracy and speed by eliminating dependency on sense timing and expanding the read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional read circuit is used for resistance change type memory, then the read operation can be performed, but the read speed is limited and read errors increase due to variations in resistance values and manufacturing variations
Solution Approach 1:
The patent changes the parameter domain of the read signal from time domain to frequency domain by extracting high-frequency components. This parameter transformation allows the system to operate in a domain where signal differentiation is enhanced, enabling faster read operations with improved reliability by reducing sensitivity to resistance variations and manufacturing tolerances.
Solution Approach 2:
The patent replaces the conventional time-domain sensing mechanism with a frequency-domain filtering mechanism. By substituting the traditional read approach with high-pass filtering and peak detection, the system achieves both faster read speed and reduced read errors without relying on precise timing or resistance value stability.
2Measurement precision
If conventional read timing is used, then the read operation can be completed, but the sense timing dependency limits read accuracy and increases read errors
Solution Approach 1:
The patent extracts the high-frequency component from the read signal using a high-pass filter, separating the useful signal information from the timing-dependent components. This extraction eliminates the need for precise sense timing control, as the peak detection method inherently identifies the signal maximum regardless of timing variations, thereby improving read accuracy while reducing control complexity.
Solution Approach 2:
The patent introduces a peak hold circuit as an intermediary between the filter circuit and the sense amplifier. This intermediary component captures and holds the peak value of the filtered signal, decoupling the sensing operation from timing constraints and providing a stable reference for accurate data retrieval without requiring complex timing control.
3Speed
If the read margin is kept small for high-speed operation, then read speed is improved, but read errors increase due to variations in resistance values
Solution Approach 1:
The patent transitions the read operation from the time dimension to the frequency dimension by employing high-pass filtering. This dimensional change allows the system to achieve both high speed and large read margin simultaneously, as the frequency-domain representation enhances signal differentiation and makes the read operation less sensitive to resistance value variations and manufacturing tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the read accuracy and speed of resistance change type memory devices by converting high-frequency components into DC signals, reducing read errors and maintaining high sense margins, thus improving overall operation characteristics.
Implementation Method 1
a filter circuit configured to output a second signal in a first frequency domain from a first signal, the first signal being outputted from the memory cell by the read pulse
Implementation Method 2
a hold circuit configured to hold a peak value of the second signal
Data Source
AI summary
According to one embodiment, a memory device includes: a memory cell; a read driver configured to supply a read pulse to the memory cell at the time of a read operation for the memory cell; a filter circuit configured to output a second signal in a first frequency domain from a first signal, the first signal being outputted from the memory cell by the read pulse; a hold circuit configured to hold a peak value of the second signal; and a sense amplifier circuit configured to read data from the memory cell based on the peak value.