Memory Read-Level Correction Using ECC Feedback and Design Matrices

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Solution Overview

Problem

The threshold voltage of memory cell transistors in memory systems can change due to various factors, leading to errors in data read operations, and existing correction methods require large buffers or complicate control, reducing efficiency.

Innovation Solution

A memory system and method that uses a design matrix and model matrix to correct read level values by adjusting the read level based on error correction codes, allowing for efficient correction without large buffers or complex control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional correction methods are used to correct read level values, then threshold voltage changes can be compensated, but large buffers or complex control mechanisms are required, reducing system efficiency

Engineering Contradiction:
Improveread operation accuracyVSAvoidbuffer size and control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory cell array is divided into multiple blocks, with designated correction blocks used specifically for read level correction operations. This segmentation allows correction operations to be performed in dedicated regions without interfering with normal data storage and retrieval operations, reducing the need for large buffers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system uses error correction codes (ECC) stored in the memory to automatically calculate and apply read level corrections. The memory system performs self-diagnosis and self-correction by utilizing its own stored data, eliminating the need for external complex control mechanisms or large correction buffers.

Inventive Principle:
Principle #25Self-service

2Ease of operation

If read level values are not corrected, then system operation is simple, but errors occur in data read operations due to threshold voltage changes

Engineering Contradiction:
Improvesystem operation simplicityVSAvoiddata read accuracy
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

Read level correction values are calculated and stored in advance during manufacturing or initialization. These pre-calculated correction values are then applied automatically during normal read operations, maintaining system simplicity while ensuring data accuracy without requiring complex real-time correction logic.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses error correction codes to detect read errors caused by threshold voltage drift and automatically adjusts read levels based on this feedback. This closed-loop approach maintains data accuracy while keeping the control mechanism relatively simple by leveraging existing ECC infrastructure.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20260018214A1Memory system and method
Publication Date: 2026.01.15 KIOXIA CORP
  • US20260018214A1 patent drawing
  • US20260018214A1 patent drawing
  • US20260018214A1 patent drawing

AI summary

A memory controller reads data from a first storage area of each of N memory cell groups based on changing a set value of a first read level in a change pattern defined by each different row of a first design matrix. The memory controller calculates a plurality of first coefficients of a first model formula based on the number of error bits in the data read from the first storage area of each of the N memory cell groups and a first model matrix. The memory controller calculates a correction amount of the set value of the first read level based on calculated values of the plurality of first coefficients and the first model formula. The memory controller updates the set value of the first read level based on the correction amount.