Memory Read Level Shifter Circuit for Faster Signal Crossing
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Solution Overview
Problem
Level shifter circuits in on-chip memory systems introduce timing penalties due to their design, affecting the performance of System-on-Chip (SOC) by causing delays and degrading the slope of output signals, which in turn impacts the access time and cycle time of memory operations.
Innovation Solution
A novel level shifter circuit design that includes a NMOS transistor, a PMOS transistor, a digital logic circuit, and inverters, where the drain of the NMOS and PMOS transistors are connected to a latched node that toggles only during read operations, and the gate of the digital logic circuit receives a switch enable signal, optimizing the level shifter to reduce delay and improve signal slope by utilizing existing differential input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional level shifter circuit is used to ensure robustness of SOC design when signals cross power domains, then reliability is improved, but access time increases due to timing penalties and gate delays
Solution Approach 1:
The patent implements dynamic control of the level shifter circuit by using a switch enable signal that activates the circuit only during read operations. The gate of the first digital logic circuit receives this switch enable signal, allowing the circuit to transition between active and inactive states dynamically, thereby reducing access time while maintaining reliability when needed.
Solution Approach 2:
The patent uses a latched node that toggles only during read operations to prepare the circuit state in advance. The latched node is set before the actual read operation occurs, allowing the level shifter to be pre-configured and ready, which reduces the timing penalty during the actual access operation.
2Adaptability or versatility
If a conventional level shifter circuit is used to enable signal crossing between power domains, then adaptability is improved, but the slope of output signals degrades causing performance loss
Solution Approach 1:
The patent segments the level shifter circuit into distinct functional blocks: a first PMOS transistor, a first digital logic circuit, and a second digital logic circuit. This segmentation allows each block to be optimized independently, with the first digital logic circuit specifically designed to improve signal slope while maintaining the adaptability of the overall circuit for signal crossing between power domains.
3Reliability
If a conventional level shifter circuit is used in memory operations, then robustness is maintained, but cycle time increases due to timing penalties
Solution Approach 1:
The patent implements periodic activation of the level shifter circuit using a switch enable signal that is activated only during read operations and remains inactive during other operations. This periodic action reduces the overall cycle time by eliminating unnecessary delays during write operations and other non-read memory operations, while maintaining robustness when the circuit is actively engaged.
Data Source
AI summary
An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the A output of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.