Memory Read Polarity Switching to Suppress Read Disturbance
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Solution Overview
Problem
Existing memory devices experience read disturbance during the read mode, where the data value or logic value of memory cells unintentionally changes due to structural and operational characteristics, leading to unintended resistance state shifts.
Innovation Solution
A memory device and system that includes voltage selection circuits to supply high and low voltages based on a flag signal, alternating the direction of cell current flow during read operations to suppress read disturbance, using a forward and reverse read operation based on read count information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If read operations are performed repeatedly on memory cells, then data is accessed, but read disturbance causes unintended resistance state changes
Solution Approach 1:
The patent applies periodic action by alternating the direction of cell current flow between forward and reverse directions based on read count information. When read count is N times or less, current flows in forward direction; when read count exceeds N times, current flows in reverse direction. This periodic alternation prevents cumulative read disturbance while maintaining continuous read operation capability.
2Measurement precision
If voltage is applied to read memory cells, then data is read, but threshold voltage deterioration occurs leading to abnormal distribution
Solution Approach 1:
The patent applies inversion by reversing the direction of cell current flow when read count exceeds threshold N. Instead of always applying voltage in the same direction, the system inverts the voltage polarity by switching between forward and reverse read operations. This inversion compensates for threshold voltage deterioration and maintains abnormal distribution within acceptable ranges.
3Speed
If memory cells are read using conventional methods, then read speed is maintained, but read disturbance accumulates over time
Solution Approach 1:
The patent applies feedback by using read count information to dynamically control the direction of cell current flow. The system monitors the number of read operations and adjusts the voltage polarity accordingly - forward direction for reads N times or less, reverse direction for reads exceeding N times. This feedback mechanism suppresses read disturbance accumulation while maintaining read speed.
Data Source
AI summary
A memory device includes a memory cell array including memory cells, a first voltage selection circuit suitable for supplying one of a high voltage and a low voltage to one end of the memory cell array in response to a flag signal indicating a forward read operation or a reverse read operation in a read mode, a logic value of the flag signal being determined based on read count information, a second voltage selection circuit suitable for supplying the other voltage of the high voltage and the low voltage to the other end of the memory cell array in response to the flag signal in the read mode, and a read circuit coupled to one of the one end and the other end of the memory cell array and reading data stored in a memory cell selected from the memory cells in the read mode.