Memory Read Voltage Threshold Tracking for Shifting Voltage Distributions
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Solution Overview
Problem
Existing memory sub-systems face challenges in accurately adjusting read voltage thresholds due to shifts in threshold voltage distributions caused by random workloads and operating conditions, leading to inefficiencies in read operation latency and accuracy.
Innovation Solution
Utilizing memory device-originated metrics, such as failed byte count and failed bit count, to iteratively adjust read voltage thresholds through calibration operations, minimizing latency and maximizing accuracy by tracking voltage distribution shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional fixed read voltage thresholds are used, then device complexity is low, but measurement precision deteriorates due to voltage distribution shifts
Solution Approach 1:
The patent implements feedback by using memory device-originated metrics (failed byte count, failed bit count) from read operations to iteratively adjust read voltage thresholds. The controller receives these metrics, performs calibration operations to determine threshold adjustments, and applies the adjustments to improve subsequent read accuracy, creating a closed-loop feedback system that adapts to voltage distribution shifts
Solution Approach 2:
The memory device serves itself by generating the metrics needed for its own calibration. The device-originated metrics from normal read operations are used to calibrate the read voltage thresholds without requiring external test equipment or additional calibration hardware, enabling the system to self-adjust and maintain accuracy autonomously
2Measurement precision
If iterative calibration operations are performed, then measurement precision improves, but productivity deteriorates due to increased latency
Solution Approach 1:
The patent performs preliminary calibration operations using readily available device-originated metrics from normal read operations before final threshold determination. By utilizing metrics that are already generated during regular memory operations, the calibration process prepares the system in advance without requiring separate, time-consuming measurement steps, thus reducing the impact on overall read throughput
Solution Approach 2:
The calibration system serves multiple functions: it maintains read voltage threshold accuracy while operating within existing memory read/write operations. The same read operations that retrieve data also generate the metrics needed for calibration, making the calibration process multi-functional and reducing the need for dedicated calibration operations that would increase latency
3Measurement precision
If voltage threshold adjustments are made frequently, then measurement precision is maintained, but loss of energy increases due to additional calibration operations
Solution Approach 1:
The patent maintains continuous voltage threshold accuracy by utilizing metrics from ongoing read operations rather than performing discrete, energy-intensive calibration cycles. The calibration process continuously adapts to voltage distribution shifts using data already being collected during normal memory operations, eliminating the need for periodic shutdowns or dedicated calibration phases that would consume additional energy
Data Source
AI summary
Described are systems and methods for memory read threshold tracking based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first value of a metric characterizing threshold voltage distributions of a subset of a set of the plurality of memory cells; determining a first voltage threshold adjustment value; receiving a second value of the metric; determining a second voltage threshold adjustment value; and applying the second voltage threshold adjustment value for reading the set of the plurality of memory cells.