Memory Cell Redistribution Layer for Capacitor-Pillar Alignment
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Solution Overview
Problem
In memory device fabrication, the arrangement of cylindrical capacitors on top of transistors in a rectangular pattern often results in poor electrical properties due to the bottom electrodes of the capacitors not being directly on top of the transistor pillars, leading to ineffective charge storage and unreliable performance.
Innovation Solution
The implementation of a redistribution layer between transistors and capacitors enables improved electrical coupling by ensuring the bottom electrode of the capacitor is properly accessed via the transistor pillar, enhancing the electrical properties and reliability of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cylindrical capacitors are arranged on top of transistors in a rectangular pattern, then the memory device structure is formed, but poor electrical properties occur due to misalignment between bottom electrodes and transistor pillars
Solution Approach 1:
A redistribution layer is introduced as an intermediary component between the capacitor bottom electrodes and the transistor pillars. This redistribution layer realigns the electrical connections, ensuring that the bottom electrodes are properly coupled to the transistor pillars despite the rectangular arrangement of capacitors. The redistribution layer acts as a mediator that corrects the misalignment issue without requiring changes to the capacitor or transistor structures themselves.
2Ease of manufacture
If bottom electrodes of capacitors are not directly on top of transistor pillars, then manufacturing is simplified, but charge storage becomes ineffective and performance becomes unreliable
Solution Approach 1:
The redistribution layer introduces an additional dimensional layer in the vertical stack, allowing the bottom electrodes to be offset horizontally from the transistor pillars while still achieving proper electrical connection through the redistributed pathways in the redistribution layer. This dimensional approach enables the capacitor array to maintain its simplified rectangular layout while correcting the alignment issue through the intermediate redistribution layer.
Data Source
AI summary
A memory device includes an array of memory cells. A memory cell includes a transistor with a pillar that includes an upper source/drain, a lower source/drain, and a channel between the upper source/drain and the lower source/drain. The transistor includes a gate that is part of a gate line and that is proximate to the channel. The memory cell includes a capacitor having a bottom electrode, an insulator, and a top electrode. The memory cell includes a conductive contact region that couples the transistor and the capacitor and that includes the upper source/drain, a first conductive region having a right surface that abuts the upper source/drain and having a left surface that contacts a first insulator line, and a second conductive region having a left surface that abuts the upper source/drain and having a right surface that contacts a second insulator line that is parallel to the first insulator line.