Semiconductor Memory Redundancy Bitline Repair
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Solution Overview
Problem
NOR flash memory devices face yield reduction due to defective memory cells, as they require replacement of bitlines connected to fail cells with redundancy bitlines, which is challenging with increasing integration density.
Innovation Solution
The semiconductor memory device includes a main cell array region with redundancy and dummy cell array regions positioned closer to the main cell array, allowing for the selection and replacement of main bitlines with redundancy bitlines based on proximity, enhancing operational characteristics and repair efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density of semiconductor devices is increased, then productivity is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple redundancy bitline regions (first redundancy bitline region with first redundancy bitline, second redundancy bitline region with second redundancy bitline) at different locations surrounding the main cell array region. This allows the system to have repair capabilities prepared in advance, enabling selection of the most appropriate redundancy bitline based on the location of the defective cell, thereby maintaining high yield even as integration density increases and defect likelihood rises.
2Reliability
If a fail cell is generated in the main cell array region, then a global bitline must be replaced with a redundancy bitline, but device complexity increases due to multiple redundancy regions
Solution Approach 1:
The patent applies local quality by creating different types of redundancy bitline regions positioned at different locations around the main cell array region. Each redundancy region is optimized for repairing defects in specific areas - for example, the first redundancy bitline region may be optimally positioned for repairing defects in one quadrant while the second redundancy bitline region serves another quadrant. This localized approach enables efficient defect repair while maintaining manageable complexity through spatial organization.
Data Source
AI summary
A semiconductor memory device includes a main cell array region, a first redundancy cell array region and a first dummy cell array region that are formed at one side of the main cell array region, and a second redundancy cell array region and a second dummy cell array region that are formed at the other side of the main cell array region. The first redundancy cell array region includes a first redundancy bitline, and the first dummy cell array region includes first dummy bitlines. The second redundancy cell array region includes a second redundancy bitline, and the second dummy cell array region includes second dummy bitlines. The first and second redundancy cell array regions are disposed closer to the main cell array region than the first and second dummy cell array regions.