Memory Device Redundancy Testing via Coupling Circuit
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Solution Overview
Problem
Current methods for testing and repairing DRAM semiconductor memory devices with redundancy face challenges in ensuring the quality of redundancy elements, leading to potential failures due to insufficient testing and increased costs from additional testing requirements.
Innovation Solution
A method and device that couple regular memory cells with redundant cells using a coupling circuit for parallel testing and stress evaluation, allowing for the identification and replacement of defective cells with tested redundant cells, ensuring high-quality repairs without additional test effort.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If redundant memory cells are used to replace defective cells, then repair capability is improved, but the quality of redundancy elements cannot be ensured
Solution Approach 1:
The patent applies preliminary action by testing and validating redundant memory cells during the manufacturing process before they are needed for repair. The method includes coupling regular and redundant memory cells, applying stress loads, and performing tests to identify and deactivate defective redundant cells in advance, ensuring only qualified redundancy elements remain available for future repairs.
2Reliability
If additional testing of redundant cells is performed, then quality of redundancy elements is improved, but testing costs and time increase
Solution Approach 1:
The patent merges the testing of regular and redundant memory cells into a single integrated process. By coupling the memory cell under test with its corresponding redundant cell and applying stress simultaneously, the method enables parallel testing that validates both cells without requiring separate test sequences, thereby improving efficiency while maintaining quality.
Solution Approach 2:
The patent implements continuity of useful action by performing redundant cell testing during the normal manufacturing test process rather than as a separate additional step. The coupling circuit allows testing to continue seamlessly while validating redundancy elements, eliminating idle time and ensuring continuous productive use of test equipment.
3Reliability
If stress testing is applied to validate redundancy, then reliability of memory device is improved, but risk of inducing defects increases
Solution Approach 1:
The patent converts the potential harm of stress-induced defects into a benefit by using controlled stress testing to identify and deactivate defective cells before they can cause failures during operation. The stress load, which could potentially create defects, is instead used as a validation tool to reveal existing weaknesses and eliminate them through deactivation, thereby improving overall reliability.
Data Source
AI summary
A memory device and method for testing memory devices with repairable redundancy is disclosed. In one embodiment, both the regular memory area and the redundant memory area are subject to the same loads during manufacturing and test processes, and that at least one regular memory cell from a regular memory area and at least one redundant memory cell from a redundant memory area are connected with each other via a coupling circuit. The coupling circuit, in particular during the testing of the operability of the semiconductor memory device or of the memory cells, respectively, determines the state of the regular memory cell and/or the redundant memory cell. Thus, in tested and repaired semiconductor memory devices, so-called redundancy storage space for the repair of defective memory capacity can be provided for repair even in the last memory test step, including full test severity and fulfilling all and any reliability requirements for the repair of high-grade memory devices.