Memory Redundancy Controller Buffering Defect Compensation
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Solution Overview
Problem
Existing semiconductor memory devices, such as NAND type flash memory, face challenges in high-speed data reading and writing due to the time required for address pointer movement to replace defective memory cells with redundant ones, and the large peripheral circuit area required for redundancy functions, which hinders downsizing and increases costs.
Innovation Solution
A memory device with a controller that manages redundancy information to replace defective memory cells with redundant ones during data read and write operations, reducing the need for extensive peripheral circuitry and enabling faster data transfer by processing redundancy information at the controller level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address pointer movement control is performed to replace defective memory cells with redundant ones, then defective memory elements can be compensated, but data reading and writing speed decreases
Solution Approach 1:
The patent pre-loads redundancy information (mapping between defective cells and redundant cells) into a buffer memory before data operations. When a defective cell is detected, the controller immediately retrieves the corresponding redundant cell address from the buffer without performing address pointer movement, thus maintaining high-speed data access while still providing defect compensation
2Reliability
If redundancy circuits are provided in the memory device, then defective memory elements can be compensated, but the peripheral circuit area increases
Solution Approach 1:
The patent extracts the redundancy management function from the memory array itself and relocates it to the controller unit. The controller contains a buffer memory that stores redundancy information, separating the defect compensation logic from the memory cells. This reduces the peripheral circuit area within the memory device while maintaining full redundancy functionality through the external controller
Solution Approach 2:
The patent introduces a buffer memory as an intermediary between the memory array and the controller. This buffer stores pre-fetched redundancy information, acting as a mediator that eliminates the need for complex address pointer movement circuits in the memory device itself, thereby reducing peripheral circuit area while maintaining defect compensation capability
3Reliability
If address pointer movement is performed for redundancy replacement, then defective bits can be replaced, but the operation time increases
Solution Approach 1:
The system performs preliminary action by pre-loading redundancy mapping information into a buffer memory before data operations commence. This allows the controller to immediately substitute defective cell addresses with redundant cell addresses from the buffer without time-consuming address pointer movements during actual data read/write operations, significantly reducing operation time while maintaining reliable defective bit replacement
Data Source
AI summary
A memory device includes at least one memory, a controller controlling the at least one memory and a connect unit. The at least one memory includes a memory region comprising a plurality of memory cells, a redundant memory region comprising a plurality of memory cells and a redundancy information memory unit. The redundancy information memory unit stores redundancy information of the memory cells of the memory region. The controller includes a control unit. The control unit controls data read-out from the at least one memory and data to be written-in to the at least one memory according to the redundancy information stored in the redundancy information memory unit.