Concurrent Memory Redundancy for Real-Time Fault Repair
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Solution Overview
Problem
Conventional memory systems require sequential operations for fault detection and repair, which increases the time required to identify and fix errors, necessitating return of faulty integrated circuits for repair.
Innovation Solution
A memory system that enables concurrent error detection and redundancy activation, allowing error detection, isolation, and repair to occur simultaneously with read and write operations without modifying existing error detection or redundancy enable circuits, using a sequencer to manage output signals and activate error detection and redundancy enable circuits in a concurrent mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential fault detection and repair process is used, then repair can be performed with existing circuits, but memory speed is reduced and time for fault detection and repair increases
Solution Approach 1:
The patent pre-loads test vectors into the memory array before normal operation begins. During concurrent mode, these pre-loaded vectors are automatically compared with read vectors, enabling fault detection without interrupting normal memory operations. This preliminary preparation allows the system to maintain high speed while performing fault detection and repair concurrently.
2Device complexity
If sequential fault detection and repair process is used, then existing error detection and redundancy enable circuits can be used, but time for fault detection and repair increases
Solution Approach 1:
The patent enables the error detection circuit and redundancy enable circuit to operate continuously during normal memory operations rather than sequentially. The sequencer coordinates these circuits to work concurrently with read and write operations, ensuring that fault detection, isolation, and repair occur without interrupting the continuous flow of normal memory operations, thereby eliminating idle time.
3Loss of time
If concurrent mode is implemented, then fault detection and repair time is reduced, but device complexity increases due to sequencer and concurrent operation logic
Solution Approach 1:
The sequencer is designed to serve multiple functions: it controls the error detection circuit, coordinates the redundancy enable circuit, and manages the output of faulty feature identification. By making the sequencer a multi-functional control unit that handles various aspects of concurrent operation, the patent reduces the need for separate dedicated control circuits, thereby limiting the increase in overall device complexity while enabling concurrent fault detection and repair.
4Reliability
If concurrent error detection and redundancy activation are enabled, then real-time error correction is achieved, but output signal management becomes complex
Solution Approach 1:
The sequencer acts as an intermediary between the concurrent operations of error detection, faulty feature identification, and redundancy activation. It receives outputs from these parallel circuits and sequences them in the correct order, mediating the complex interactions and ensuring that output signals are managed systematically. This intermediary role simplifies the overall system architecture by providing a single coordination point for concurrent operations.
Data Source
AI summary
A memory includes an error detection circuit that identifies a faulty feature in an array of memory cells within the memory. A redundancy enable circuit functions to replace the faulty feature with a redundant feature. The error detection circuit and the redundancy enable circuit function concurrently with a read operation on the array of memory cells.