Semiconductor Memory Reference Voltage Test via Data Terminal

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Solution Overview

Problem

Conventional semiconductor memory device testing methods fail to accurately perform operation tests using the original reference voltage after fine adjustment, leading to decreased test accuracy and increased manufacturing costs due to the need for multiple trimming processes and complex testers.

Innovation Solution

A semiconductor memory device and test method that allow for the internal generation of the original reference voltage by measuring and fine-adjusting it for each chip, enabling individual code input through data input and output terminals, even when clock, address, and command terminals are connected in common, thus simplifying the testing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a reference voltage is externally applied equal to the design value, then the operation test can be performed in design conditions, but the original reference voltage after fine adjustment cannot be correctly realized, decreasing test accuracy

Engineering Contradiction:
Improveease of operation testVSAvoidtest accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The semiconductor memory device itself generates and provides the reference voltage needed for testing. The reference voltage generating circuit within the device creates the original reference voltage after fine adjustment, and this voltage is supplied to the testing circuit through the data input and output terminal. This self-service approach eliminates the need for external reference voltage application while ensuring the test uses the actual operating reference voltage.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The data input and output terminal is made multi-functional by enabling it to receive not only data signals but also the reference voltage through the switching unit. This allows the same terminal to serve dual purposes: normal data I/O operations and reference voltage supply for testing, thereby simplifying the overall test setup without requiring additional dedicated terminals or complex external equipment.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If fuse trimming is performed for fine adjustment and then another trimming is needed after defective address detection, then defective cells can be replaced, but manufacturing cost increases and electrode pad damage increases reducing reliability

Engineering Contradiction:
Improvedevice reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The fine adjustment of the reference voltage is performed preliminarily during the manufacturing process using fuse trimming. The switching unit is configured in advance to enable the data input and output terminal to receive this pre-adjusted reference voltage. This preliminary action ensures that the same reference voltage used during operation is used during testing, eliminating the need for subsequent trimming operations after defective address detection.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If individual codes are input to chips for temporary fine adjustment, then accurate testing using original reference voltage is possible, but the tester becomes substantially complex

Engineering Contradiction:
Improvetest accuracyVSAvoidtester complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The reference voltage is extracted from the data input and output terminal through the switching unit and supplied to the testing circuit. This extraction eliminates the need for complex external code input mechanisms and individual chip adjustments. The switching unit automatically routes the reference voltage from the terminal to the appropriate circuit blocks, simplifying the tester configuration while maintaining accurate testing capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS7558135B2Semiconductor memory device and test method thereof
Publication Date: 2009.07.07 NVIDIA CORP
  • US7558135B2 patent drawing
  • US7558135B2 patent drawing
  • US7558135B2 patent drawing

AI summary

When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used as an internal clock ICLK. Accordingly, during a test in a wafer state, a clock signal can be received from the data input and output terminal DQ, even when a clock terminal, an address terminal, and a command terminal are connected in common to plural semiconductor memory devices. Therefore, a code for artificially performing a fine adjustment of a reference voltage can be individually supplied for each chip.