Volatile Memory Refresh Control Circuit Power Optimization
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Solution Overview
Problem
Conventional refresh control circuits for DRAMs are complex and inefficient, particularly at room temperature, due to the need for multiple current generating and timing circuits, leading to excessive power consumption.
Innovation Solution
A simplified refresh control circuit that compares memory voltages to a statistically determined threshold voltage, using a differential amplifier and digital circuit to control self-refresh operations, and includes a switch to selectively connect memory cells to power voltage based on voltage levels, reducing power consumption by optimizing refresh intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple current generating circuits and timing circuits are used to control refresh periods, then refresh control precision is improved, but device complexity increases and power consumption increases
Solution Approach 1:
The patent combines multiple separate circuits (current generating circuits, timing circuits, temperature sensing circuits) into a single integrated refresh control circuit. The refresh control circuit directly compares memory cell voltage levels with threshold voltages to determine refresh timing, eliminating the need for separate temperature sensing and timing generation circuits while maintaining accurate refresh control.
Solution Approach 2:
The patent extracts the essential function of refresh control from complex multi-circuit systems and implements it through a simplified voltage comparison mechanism. By removing unnecessary intermediate circuits and keeping only the core voltage comparison function, the design achieves accurate refresh control with minimal circuitry.
2Measurement precision
If multiple current generating circuits and timing circuits are used to control refresh periods, then refresh control precision is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple power-consuming circuits into a single low-power refresh control circuit that performs voltage comparisons. This integration eliminates redundant power consumption from separate current generating circuits and timing circuits while maintaining the necessary refresh control precision.
Solution Approach 2:
The patent uses simple voltage comparison logic instead of complex, power-intensive timing and temperature sensing circuits. The refresh control relies on direct voltage level detection rather than continuous monitoring and processing, significantly reducing power consumption while maintaining functional accuracy.
3Use of energy by moving object
If refresh interval is prolonged to decrease number of refresh operations, then power consumption decreases, but data retention reliability deteriorates
Solution Approach 1:
The patent implements dynamic refresh interval adjustment based on detected voltage levels. When voltage levels indicate stable data retention, the refresh interval is extended; when voltage levels approach threshold values indicating potential data loss, the refresh interval is shortened. This dynamic adaptation optimizes both power consumption and data retention reliability.
Solution Approach 2:
The refresh control circuit continuously monitors memory cell voltage levels and uses this feedback to adjust refresh timing. The comparison between actual voltage levels and threshold voltages provides real-time feedback that determines whether to perform refresh operations or extend the refresh interval, balancing power savings with data integrity.
4Reliability
If refresh operations are increased to maintain data retention, then data retention reliability is improved, but power consumption increases
Solution Approach 1:
The patent uses dynamic refresh scheduling that adapts to actual memory cell conditions. Instead of fixed frequent refresh operations, the system adjusts refresh frequency based on detected voltage levels, performing refresh operations only when necessary to maintain data integrity, thereby reducing unnecessary power consumption.
Solution Approach 2:
The patent applies refresh operations selectively rather than uniformly to all memory cells at fixed intervals. By performing refresh operations only when voltage comparison indicates data retention is at risk, the system achieves adequate data protection with minimal refresh operations, reducing overall power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces power consumption by simplifying the circuit structure and optimizing refresh periods, especially at room temperature, while maintaining effective data retention.
Implementation Method 1
a differential amplifier 12 configured to amplify a differential voltage between an inverting input terminal to which the memory voltage is input and a non-inverting input terminal to which a reference voltage is input
Data Source
AI summary
A refresh control circuit of a volatile semiconductor memory device is provided, where the volatile semiconductor memory device includes a plurality of memory cells respectively having a select transistor and a memory element, and the refresh control circuit of the volatile semiconductor memory device includes: a first comparison part, which compares a memory voltage of the memory cell of the volatile semiconductor memory device that is different to a general-memorizing memory cell with a specified threshold voltage, and outputs a comparison result signal, and stops self refresh of the memory cell until the memory voltage is decreased to be smaller than the specified threshold voltage. The memory cell is formed in a region adjacent to an array of the general-memorizing memory cell.