Memory Refresh Erase Control for Secure Tenant Data Removal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in securely erasing user data without revealing physical row addresses, which can compromise data security and increase latency for other users.
Innovation Solution
Implementing a selectable memory system erase function that overwrites user data during a refresh operation by mapping physical row addresses to a mode register, allowing secure erasure without affecting latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If user data is erased by enabling host system to overwrite or memory system controller to directly perform re-write operations, then data security is improved, but latency for other users increases and physical row addresses are revealed
Solution Approach 1:
The patent applies preliminary action by setting erase bits in the mode register before the actual refresh operation occurs. The controller prepares the memory device by configuring the mode register with row address information that identifies which rows should be erased, so that when the refresh operation is initiated, the erasure process is already predetermined and can proceed without additional latency-inducing steps.
Solution Approach 2:
The patent introduces the mode register as an intermediary mechanism between the controller and the memory array. The mode register acts as a mediator that stores row address information and controls the refresh operation to perform both reading and overwriting functions. This intermediary allows the system to erase data securely without directly exposing physical row addresses or causing increased latency, as the mode register handles the coordination internally.
2Reliability
If traditional erase operations are performed by overwriting data, then data security is improved, but physical row addresses are revealed to bad actors
Solution Approach 1:
The mode register serves as an intermediary that masks the physical row addresses from external observation. When the controller needs to erase data, it sets bits in the mode register corresponding to the rows to be erased, but the actual physical addresses are not exposed during the process. The refresh operation uses the mode register information internally to identify and overwrite the target rows without revealing their physical locations to potential attackers.
Solution Approach 2:
The patent changes the operational parameter of the refresh operation to include an erase function. By modifying the refresh operation's behavior based on the mode register settings, the system can perform erasure without using traditional overwrite methods that would expose addresses. The refresh operation's dual function (normal refresh and erase) is controlled by the state of the mode register, allowing secure erasure through parameter modification rather than address exposure.
Data Source
AI summary
Methods, systems, and devices for selectable memory system erase function are described. A user of a multitenancy memory system may request to vacate the memory system. A multitenancy controller may transmit an indication to erase data from a memory region associated with the user to a controller of the memory system. The controller may set bits of a mode register corresponding to the memory region to an erase value and other bits of the mode register corresponding to other memory regions to a normal value. The data may be erased from the memory region during the refresh cycle, while data from the other memory regions may be normally refreshed, according to the value of the bits in the mode register. The controller may indicate to the multitenancy controller that the data has been erased, and the multitenancy controller may enable the user to vacate from the memory system.