Memory Cell Refresh Using Redundancy Columns for Row Hammer
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Solution Overview
Problem
Existing semiconductor memory devices face issues with data loss due to the row hammering phenomenon, where memory cells coupled to specific word lines experience damage from excessive activations, necessitating additional target refresh operations.
Innovation Solution
The memory device allocates memory cells to unused columns in a redundancy cell area for row-hammer cells, utilizing redundancy column selection lines and a refresh control circuit to select target addresses based on access counting data, optimizing row hammer defense and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal refresh operation is performed on all word lines, then data retention is maintained, but power consumption increases and row hammering vulnerability persists
Solution Approach 1:
The patent implements target refresh operation that selectively refreshes only specific word lines (target word lines) that are vulnerable to row hammering, rather than refreshing all word lines uniformly. This local quality approach concentrates refresh resources on high-risk areas while reducing overall power consumption by skipping low-risk word lines.
Solution Approach 2:
The patent uses access counting values stored in row-hammer cells to identify which word lines have been accessed frequently and are therefore vulnerable to row hammering. This feedback mechanism dynamically determines which word lines require refresh, enabling adaptive power management based on actual usage patterns.
2Reliability
If redundancy cell area is fully utilized for repair, then defect coverage is maximized, but availability for row-hammer tracking is reduced
Solution Approach 1:
The patent divides the redundancy cell area into multiple segments: some columns are allocated for repair functions (redundancy columns) while other columns are allocated for row-hammer tracking (row-hammer columns). This segmentation allows both repair and row-hammer tracking functions to coexist within the same redundancy cell area without interfering with each other.
Solution Approach 2:
The patent makes the redundancy cell area multi-functional by using different column groups for different purposes: repair operations and row-hammer tracking. The same physical redundancy structure serves dual purposes, maximizing resource utilization while maintaining both defect coverage and row-hammer defense capabilities.
3Measurement precision
If access counting data is stored in separate dedicated cells, then tracking accuracy is improved, but device area increases
Solution Approach 1:
The patent merges the access counting function with the existing row-hammer cell structure. Instead of creating separate dedicated counting cells, the patent utilizes the row-hammer cells (which are part of the redundancy cell area) to store both repair information and access counting values. This combining approach maintains tracking accuracy while avoiding additional area overhead.
Data Source
AI summary
A memory device includes: a memory cell region including normal cells coupled to normal column selection lines, and row-hammer cells and redundancy cells respectively coupled to redundancy column selection lines; a repair control circuit configured to provide repair addresses and row-hammer flag signals, corresponding to repair information, according to a row address; and a column control circuit configured to activate at least one of the redundancy column selection lines according to the row-hammer flag signals or a comparison result of a column address and the repair addresses.