Memory Page Refresh Warnings for Read-Disturb Data Integrity

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Solution Overview

Problem

Semiconductor memory devices face data integrity issues due to read disturbance and data retention, leading to failed bits during data reading, which existing error-correcting codes struggle to correct effectively, necessitating additional monitoring and refresh operations to maintain data reliability.

Innovation Solution

Implementing a system within semiconductor devices that monitors data integrity by performing logic operations on specific data stored in memory pages, counting bits, and generating data refresh warnings when criteria are met, allowing for targeted data refresh operations to maintain data reliability without additional read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional read operations are performed to monitor data integrity, then data accuracy can be detected, but read disturbance increases and data integrity deteriorates

Engineering Contradiction:
Improvedata integrity detection accuracyVSAvoidread disturbance
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent performs logic operations on specific data patterns (e.g., all-ones or all-zeros patterns) before normal read operations to establish baseline bit counts. This preliminary action creates reference values that enable subsequent data integrity monitoring without requiring additional read operations, thus avoiding read disturbance while maintaining detection accuracy

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces logic operation results as an intermediary mechanism. Instead of directly reading memory data to check integrity (which causes read disturbance), the system performs logic operations on the data and analyzes the results. This intermediary approach allows indirect monitoring of data integrity without the harmful side effect of repeated reads

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If additional monitoring operations are implemented to detect data integrity, then data reliability improves, but device complexity and operation overhead increase

Engineering Contradiction:
Improvedata reliabilityVSAvoidmonitoring operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges data integrity monitoring with existing CIM (Computing in Memory) logic operations. By combining the monitoring function with regular computation operations, the system achieves data reliability improvement without adding separate monitoring operations, thus avoiding increased device complexity and operation overhead

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes logic operation circuits serve dual purposes: performing computational functions and simultaneously monitoring data integrity. This multi-functionality allows the same hardware to achieve both data processing and reliability monitoring, eliminating the need for dedicated monitoring circuitry and reducing overall device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If frequent data refresh operations are performed to maintain data integrity, then data retention improves, but productivity and operation efficiency decrease

Engineering Contradiction:
Improvedata retentionVSAvoidoperation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements a feedback mechanism where logic operation results provide information about data quality. Based on this feedback, the system intelligently determines whether refresh operations are needed, rather than performing frequent unconditional refreshes. This selective approach maintains data retention while preserving operation efficiency by avoiding unnecessary refresh operations

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12020741B2Managing data refresh in semiconductor devices
Publication Date: 2024.06.25 MACRONIX INTERNATIONAL CO LTD
  • US12020741B2 patent drawing
  • US12020741B2 patent drawing
  • US12020741B2 patent drawing

AI summary

Methods, devices, and systems for managing data refresh for semiconductor devices are provided. In one aspect, a semiconductor device includes a memory cell array having a plurality of blocks each including multiple pages and one or more integrated circuits coupled to the memory cell array. The one or more integrated circuits are configured to: read specific data from a page of a block in the memory cell array, perform a logic operation on the specific data in the page to obtain a logic operation result, count a number of bits having a specific value among the logic operation result, determine whether the number of bits is within a data refresh criterion for the page, and in response to determining that the number of bits is outside of the data refresh criterion, generate a data refresh warning message for the page in the block.