Memory Region Test-Reading Periods Based on Trust Levels
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Solution Overview
Problem
Existing memory systems face inefficiencies in operation due to uniform test-reading periods applied across all memory regions, leading to unnecessary test-readings and reduced operation speed, as they do not account for varying data retention levels across different memory regions.
Innovation Solution
Implementing a method where each memory region is assigned an individual test-reading period based on its computed trust level, determined by error correction values, to optimize when test-readings are performed and reduce data reclamation needs, thereby enhancing overall system operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform test-reading periods are applied across all memory regions, then data retention reliability is maintained, but operation speed decreases due to unnecessary test-readings
Solution Approach 1:
The patent applies different test-reading periods to different memory regions based on their individual data retention characteristics. Each memory region is assigned a customized test-reading period that matches its specific retention level, rather than using a uniform period across all regions. This local differentiation eliminates unnecessary test-readings in regions with longer retention while maintaining reliability in regions with shorter retention.
Solution Approach 2:
The patent changes the test-reading period parameter dynamically based on measured data retention levels. By computing trust levels from error correction values and using these to set appropriate test-reading periods, the system adapts the timing parameter to match actual memory region characteristics, optimizing both reliability and speed.
2Reliability
If frequent test-readings are performed on all memory regions, then data retention reliability is ensured, but operation rate decreases due to increased test-reading overhead
Solution Approach 1:
The patent implements localized test-reading strategies where each memory region receives test-readings at frequencies matched to its specific data retention characteristics. Memory regions with superior retention experience fewer test-readings, while regions with poorer retention receive more frequent testing, optimizing the balance between reliability and operation rate.
Solution Approach 2:
The patent applies partial testing action by performing test-readings only when necessary based on computed trust levels. Rather than uniformly testing all memory regions at maximum frequency, the system performs test-readings at the minimum necessary frequency for each region, reducing overall overhead while maintaining reliability.
3Productivity
If individual test-reading periods are assigned based on trust levels, then operation rate improves by reducing unnecessary test-readings, but system complexity increases
Solution Approach 1:
The patent performs preliminary error correction operations and trust level computations during initial memory operations. By pre-computing trust levels and setting appropriate test-reading periods before normal operation begins, the system avoids the need for complex real-time adjustments during operation, managing complexity while achieving optimized performance.
Solution Approach 2:
The patent uses feedback from error correction values to compute trust levels and dynamically set test-reading periods. This feedback mechanism allows the system to automatically adapt test-reading frequencies based on actual memory performance, reducing the need for manual configuration or complex control logic while improving operation rate.
Data Source
AI summary
A method of a memory system including memory regions includes performing error corrections for chunks in each of the memory regions, and computing trust levels corresponding respectively to the memory regions based on the error corrections, setting test-reading periods corresponding respectively to the memory regions, based on the trust levels for the memory regions, counting a number of normal-reading times for each of the memory regions, and managing access counts corresponding respectively to the memory regions based on the counted numbers and when an access count for a first memory region among the memory regions reaches a time corresponding to a test-reading period for the first memory region, performing one or more test-readings for the first memory region.