Memory Cell Repair and Block ECC for Multiple Failures

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Solution Overview

Problem

Memory devices experience errors due to failing memory cells, which existing error correcting codes struggle to effectively identify and correct, especially when multiple cells fail simultaneously.

Innovation Solution

The implementation of a method to replace selected failing memory cells with repair memory cells and utilize error correcting codes to correct data read from other failing cells, identifying and grouping memory cells to efficiently manage and correct errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correcting codes are used to correct errors in memory cells, then data integrity is improved, but the ability to handle multiple simultaneous failures deteriorates

Engineering Contradiction:
Improvedata integrityVSAvoidability to handle multiple failures
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The memory array is divided into multiple blocks, with each block having its own error correction code. This segmentation allows the system to independently manage and correct errors in each block, improving the ability to handle multiple simultaneous failures without compromising overall data integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different error correction strategies are applied to different blocks based on their specific failure characteristics. Blocks with single failures use standard ECC, while blocks with multiple failures use alternative correction methods, allowing optimized handling of various failure scenarios.

Inventive Principle:
Principle #3Local quality

2Device complexity

If conventional error correcting codes are applied to all memory blocks, then simplicity is maintained, but performance deteriorates when multiple cells fail

Engineering Contradiction:
Improveerror correction mechanismVSAvoiddata retrieval reliability
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The error correction system dynamically adapts its behavior based on the detected failure pattern. When multiple cells fail within a block, the system switches from conventional ECC to alternative correction methods, optimizing performance for the specific failure scenario while maintaining simplicity for normal operation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the error correction parameters and methods based on the number and distribution of failed cells. This allows the system to maintain conventional simple ECC for single failures but switch to enhanced correction strategies when multiple failures are detected, improving productivity without permanently increasing complexity.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If all failing memory cells are replaced with repair cells, then data retrieval reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata retrieval reliabilityVSAvoidmemory cell management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of replacing all failing cells, the system selectively replaces only those cells that are part of uncorrectable blocks. This partial replacement approach improves data retrieval reliability for critical failures while avoiding the excessive complexity of replacing every failing cell, especially when conventional ECC can handle simpler failures.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20120324298A1Memory device repair apparatus, systems, and methods
Publication Date: 2012.12.20 MICRON TECHNOLOGY INC
  • US20120324298A1 patent drawing
  • US20120324298A1 patent drawing
  • US20120324298A1 patent drawing

AI summary

Apparatus, systems, and methods are disclosed, such as those that operate within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device using a different method. Additional apparatus, systems, and methods are disclosed.