Semiconductor Memory Repair Circuit Address Timing
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Solution Overview
Problem
In semiconductor memory devices, the repair cell operates slower than normal memory cells due to delays in address generation and control signal transmission, limiting the device's I/O speed and yield, as existing repair methods do not adequately reduce the operating time of the repair controller.
Innovation Solution
A repair circuit with an address counter generating both column address signals and a repair controller that initiates the repair address signal earlier than the second column address signal, using a repair scramble unit to select the repair cell based on control signals, thereby reducing the time required for the repair operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a repair controller is used to generate repair address signals, then the repair operation can be performed, but the operating speed of the repair cell becomes slower than normal memory cells
Solution Approach 1:
The repair controller generates the repair column address signal RADD in advance before the normal column address signal COLADD reaches the cell operation block. By performing the address generation action preliminarily, the repair cell is ready to operate simultaneously with normal cells, eliminating the speed delay caused by sequential address generation.
2Productivity
If the repair controller operates later to maintain timing, then the device I/O speed specification cannot be met
Solution Approach 1:
The repair controller is activated in advance based on the first column address signal, generating the repair address signal before it is needed. This preliminary action reduces the operating time of the repair controller and allows the device to meet its I/O speed specifications despite the additional repair operation overhead.
Data Source
AI summary
An embodiment of the present invention relates to a repair circuit of a semiconductor memory device. The repair circuit includes an address counter that sequentially generates a first column address signal and a second column address signal in response to a write enable signal or a read enable signal, a repair controller that generates a repair column address signal earlier than the second column address signal in response to the first column address signal, an address latch enable signal, a command enable signal, and a write enable signal, and a repair scramble unit that selects a repair cell in response to a repair I/O control signal and the repair column address signal. If an address on which a repair operation must be performed occurs, the repair controller directly receives the write enable signal or the read enable signal and activates the repair controller earlier than a general cell using a previous address, thereby offsetting an operating time consumed in the repair controller. Therefore, the operating speed of the repair cell can become faster than that of the general cell and the operating speed of the device can be improved accordingly.