Semiconductor Memory Device Repair Column Masking
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Solution Overview
Problem
Semiconductor memory devices face limitations in operating speed due to the need for repetitive repair column masking operations and threshold voltage distribution testing, which slows down the testing process.
Innovation Solution
Implementing a method that performs repair column masking and tests threshold voltage distributions of drain select transistors in a semiconductor memory device, allowing for sequential testing without repeated repair operations, thereby enhancing operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repair column masking operations are performed repeatedly during testing, then testing completeness is improved, but operating speed deteriorates
Solution Approach 1:
The patent applies preliminary action by performing the repair column masking operation only once before the threshold voltage distribution testing, rather than repeatedly during each test phase. The control logic configures the peripheral circuit to perform repair column masking on the selected memory block, then proceeds with testing first drain select transistors and subsequently second drain select transistors while maintaining the same repair configuration, thereby eliminating redundant operations and improving speed
Solution Approach 2:
The patent implements continuity of useful action by maintaining the repair column masking result throughout the entire testing process. After the initial repair column masking operation, the same configuration is used for testing both first and second drain select transistors without interruption or repetition, ensuring continuous efficient operation while completing all necessary testing
2Measurement precision
If multiple test operations are performed sequentially on different transistors, then testing thoroughness is improved, but time consumption increases
Solution Approach 1:
The patent performs the repair column masking operation as a preliminary action before initiating the sequence of threshold voltage distribution tests. This preliminary configuration enables subsequent tests to proceed without requiring repeated setup operations, thereby reducing time consumption while maintaining thorough testing of both first and second drain select transistors
Solution Approach 2:
The patent ensures continuous useful action by maintaining the repair column masking result throughout the entire testing sequence. The same repair configuration serves for testing first drain select transistors and then second drain select transistors, eliminating idle time and redundant operations between test phases while completing all necessary measurements
Data Source
AI summary
Provided herein is a semiconductor memory device exhibiting improved operating speed and a method of operating the semiconductor memory device. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a read operation on the memory cell array. The control logic may control an operation of the peripheral circuit. The control logic may control the peripheral circuit to perform a repair column masking operation on a selected memory block of the plurality of memory blocks, perform a first test operation on first drain select transistors included in the selected memory block, perform the first test operation on second drain select transistors different from the first drain select transistors while a result of the repair column masking operation remains.