Memory Repair Control Apparatus for High-Capacity Devices
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Solution Overview
Problem
High-cost memory repair processes for high-capacity memory devices are inefficient due to the need for a fail memory with the same address space, and existing methods cannot replace rows with excessive defective bits even after allocating all redundant memory cells.
Innovation Solution
A control apparatus and method that selectively masks and retests memory blocks with excessive defective bits, using row and column repair memory blocks to replace only necessary blocks, thereby reducing the need for additional fail memory and optimizing repair processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fail memory with the same address space as the memory under test is provided to perform memory repair process for high-capacity memory, then the memory repair process can be performed, but the cost increases significantly
Solution Approach 1:
The patent extracts only the essential function of the fail memory (storing defect information) and implements it through a simplified counting and judgment mechanism rather than requiring a complete fail memory with the same address space. The counting section tracks defective bit numbers and the judgment section compares against thresholds, extracting the core repair decision-making capability without the overhead of a full fail memory structure.
Solution Approach 2:
Instead of using an expensive fail memory structure, the patent employs simple counting sections and judgment sections that use minimal resources. The counting section maintains defect counts and the judgment section uses threshold comparisons, replacing the need for complex fail memory structures with inexpensive computational logic that achieves the same repair decision functionality.
2Reliability
If all redundant memory cells are allocated to replace defective rows, then maximum repair capacity is utilized, but newly detected rows with excessive defective bits cannot be replaced
Solution Approach 1:
The patent implements dynamic repair allocation where the judgment section continuously evaluates whether to perform replacement based on current defect counts and available redundant cells. The system can adaptively decide to replace or not replace based on real-time defect detection, allowing flexible redistribution of redundant memory cells during the repair process rather than static pre-allocation.
Solution Approach 2:
The patent performs preliminary counting of defective bits in each row before making replacement decisions. The counting section accumulates defect information and the judgment section evaluates against replacement thresholds beforehand, allowing the system to plan replacement strategies in advance and allocate redundant cells optimally before actual replacement occurs, preventing situations where redundant cells are exhausted.
3Productivity
If memory blocks with excessive defective bits are replaced using repair memory blocks, then the yield of functional memory devices is improved, but the complexity of the control process increases
Solution Approach 1:
The patent segments the memory into test blocks and divides the repair control into distinct functional sections: a counting section that tracks defective bits per row, and a judgment section that decides replacement based on thresholds. This segmentation allows independent optimization of each function and simplifies the overall control logic by breaking down the complex repair decision-making into manageable, modular components.
Solution Approach 2:
The patent implements feedback mechanisms where the counting section continuously monitors defective bit numbers and feeds this information to the judgment section. The judgment section uses this feedback to dynamically adjust replacement decisions based on current defect levels and available redundant cells, creating a closed-loop control system that automatically optimizes yield without requiring complex external control logic.
Data Source
AI summary
A control apparatus controlling testing of a memory under test that includes one or more row repair memory blocks and column repair memory blocks. The control apparatus comprises a counting section that sequentially receives test results respectively indicating pass/fail of a plurality of test blocks of the memory under test, and sequentially counts, for each first-type memory block, which is a row-oriented memory block or a column-oriented memory block, a fail memory block number among second-type memory blocks; a selecting section that selects memory blocks first-type memory blocks for which the fail memory block number exceeds a reference value, such that the number of selected memory blocks is no greater than the number of first-type repair memory blocks of the memory under test; and a test control section that masks test blocks among the memory blocks selected by the selecting section and causes further testing of the memory under test.