Semiconductor Memory Repair Control Circuit Grouping
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Solution Overview
Problem
The increasing bit error rate and decreasing yield in semiconductor memory devices due to reduced manufacturing scale, which necessitates a more efficient repair operation without increasing the device size.
Innovation Solution
A semiconductor memory device with a memory cell array divided into normal and redundancy cell regions, where the normal cell region is grouped into multiple normal region groups, and a repair control circuit determines and extracts target fail addresses to control a repair operation efficiently, reducing the number of comparators and fail addresses stored and compared.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a repair scheme using redundancy resources is used to secure yield, then the yield is improved, but the size of the semiconductor memory device increases
Solution Approach 1:
The normal cell region is divided into multiple normal region groups, and the redundancy cell region is divided into multiple redundancy region groups. This segmentation allows the repair control circuit to selectively activate only the specific redundancy region group needed for repair, rather than requiring all redundancy resources to be available simultaneously, thereby reducing the overall device size while maintaining yield.
Solution Approach 2:
The fail addresses are pre-stored in the fail address storage circuit organized by normal region groups. When a failure occurs, the repair control circuit can quickly identify and activate the corresponding redundancy resources without extensive searching, enabling efficient repair operations that reduce the needed redundancy overhead and thus device size.
2Productivity
If the normal cell region is divided into multiple normal region groups with corresponding redundancy region groups, then the repair operation efficiency is improved, but the device complexity increases
Solution Approach 1:
The fail address storage circuit is designed with a universal structure that can store fail addresses for multiple normal region groups using the same storage mechanism and comparison logic. The repair control circuit uses a unified repair operation flow that works across all normal region groups, reducing the need for separate dedicated circuits for each group and thereby limiting the increase in device complexity.
Solution Approach 2:
The repair control circuit dynamically selects which redundancy region group to activate based on the input address and stored fail addresses. This dynamic selection capability allows the system to efficiently handle repairs in different normal region groups without requiring static, dedicated repair paths for each group, optimizing repair efficiency while controlling complexity through flexible control logic.
Data Source
AI summary
A semiconductor memory device a memory cell array and a repair control circuit. The memory cell array including a normal cell region and a redundancy cell region, the normal cell region including a plurality of normal region groups, and redundancy cell region configured to replace failed memory cells of the normal cell region. The repair control circuit configured to, determine a target normal region group from among the plurality of normal region groups based on an input address, extract target fail addresses from among a plurality of fail addresses based on the target normal region group, and control a repair operation based on the target fail addresses and the input address.