Memory Device Self-Repair Using Quality-Graded Redundant Rows
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Solution Overview
Problem
Conventional memory device designs fail to utilize redundant memory cell rows to replace unreliable regular memory cell rows, leading to reliability issues and inefficiencies due to reliance on external testing apparatuses.
Innovation Solution
Integration of a built-in-self-test (BIST) unit to assess the quality of both redundant and regular memory cell rows, and a built-in-self-repair (BISR) unit to replace failed regular rows with redundant rows of equal or higher quality, enhancing the memory device's reliability and reducing testing time and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional external testing apparatus is used to test memory cell rows, then testing capability is provided, but testing time and cost increase significantly
Solution Approach 1:
The memory device performs self-testing through embedded BIST units that can autonomously evaluate memory cell row quality without requiring external testing apparatus. The BIST unit tests both redundant and regular memory cell rows to determine their quality standards, enabling the device to self-diagnose and self-repair without external intervention.
Solution Approach 2:
The system performs preliminary testing of redundant memory cell rows before they are needed as replacements. By pre-evaluating the quality of redundant rows and storing this information, the system prepares replacement candidates in advance, so when a regular row fails, an appropriate redundant row is already identified and ready for immediate replacement.
2Reliability
If redundant memory cell rows are reserved only for defective regular rows, then simple replacement scheme is maintained, but unreliable but non-defective regular rows cannot be replaced
Solution Approach 1:
The system introduces quality standard parameters to evaluate and categorize memory cell rows. By testing memory rows against multiple quality standards and assigning quality indexes, the system creates a parameter-based classification that enables differentiated replacement strategies. This allows unreliable but functional rows to be identified and replaced based on their quality parameters rather than simply treating all failures equally.
Solution Approach 2:
The BIST unit provides feedback about the quality of memory cell rows by testing them and determining quality standards. This feedback information is stored and used by the BISR unit to make informed replacement decisions. The feedback mechanism enables the system to learn from testing results and make intelligent decisions about which redundant rows to allocate to which failed regular rows.
3Measurement precision
If minimal functionality test is used to identify defective rows, then defective rows can be detected, but unreliable rows that pass minimal testing remain undetected
Solution Approach 1:
The system transitions from binary pass/fail testing to multi-level quality standard evaluation. By introducing multiple quality standards and corresponding quality indexes, the system can distinguish between rows that merely pass minimal functionality tests and rows that are truly reliable. This parameter-based approach enables precise measurement of row quality and identification of unreliable rows that would otherwise be missed.
Data Source
AI summary
A system for improving reliability of a memory device includes one or more memory banks, each of which has one or more regular memory cell rows and one or more redundant memory cell rows. At least one built-in-self-test (BIST) unit is coupled to the memory banks for testing the redundant memory cell rows to determine their respective quality standards, and testing the regular memory cell rows to identify the regular memory cell row that fails to pass a predetermined quality standard. At least one built-in-self-repair (BISR) unit is coupled to the BIST unit for replacing the failed regular memory cell row with the redundant memory cell row having a quality standard equal to or higher than the predetermined quality standard. The BIST unit repeatedly tests the regular memory cell rows a number of times, with each time applying a different quality standard.