Memory Cell Reset Control for Read Disturb Mitigation
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Solution Overview
Problem
Memory cells, such as RRAM, MRAM, and flash memory, experience increased read disturb effects under higher process voltage temperature (PVT) conditions, leading to data loss and failed read operations due to higher read voltage levels and operation temperatures.
Innovation Solution
A semiconductor device configuration that includes a memory circuit, error correction code circuit, logic circuit, register circuit, and write circuit, which detects read disturb errors, generates error information, and resets memory cells using pulse signals with lower voltage levels and shorter time periods to prevent over-resetting and data loss, while allowing for separate read and reset operations to avoid conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher read voltage levels are used to improve read operation reliability, then read disturb effect increases causing data loss
Solution Approach 1:
The patent dynamically adjusts read voltage levels based on detected error patterns. When read disturb errors are detected, the system changes the read voltage parameter to a lower level for subsequent reads, thereby reducing the read disturb effect while maintaining adequate read operation reliability through adaptive parameter selection.
Solution Approach 2:
The patent implements a feedback mechanism where read operations monitor for disturb effects and feed this information back to control the read voltage level. The system detects errors indicative of read disturb, then adjusts subsequent read voltage levels accordingly, creating a closed-loop control system that balances reliability with harm reduction.
2Productivity
If higher operation temperatures are used to improve device performance, then read disturb effect increases leading to data loss
Solution Approach 1:
The patent adjusts read operation parameters including voltage levels in response to temperature variations and detected error patterns. When operating at higher temperatures where read disturb increases, the system dynamically changes the read voltage parameter to mitigate the temperature-induced disturb effect while maintaining device performance.
3Reliability
If reset operations are performed frequently to correct read disturb errors, then memory cell integrity is maintained, but over-resetting occurs causing data loss
Solution Approach 1:
The patent uses feedback from error detection to control reset operations. The system monitors read operations for specific error patterns indicative of read disturb, and only triggers reset operations when these errors are detected. This feedback-based control prevents unnecessary reset operations that would cause over-resetting, while still maintaining memory cell integrity when needed.
Solution Approach 2:
The patent applies reset operations selectively rather than continuously or excessively. By triggering resets only when error patterns indicate actual read disturb damage, the system avoids the excessive action of frequent resets that would cause over-resetting, while still providing sufficient reset action to maintain integrity when required.
4Productivity
If read and reset operations are performed simultaneously to improve efficiency, then operation speed increases, but operation conflicts occur causing data loss
Solution Approach 1:
The patent segments the memory access operations into distinct read phases and reset phases. By separating these operations in time rather than allowing simultaneous execution, the system eliminates conflicts between read and reset operations while maintaining efficient throughput through proper operation scheduling and state management.
Data Source
AI summary
A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.