Memory Cell Rewrite Path Switching for Faster Low-Power Rewriting
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Solution Overview
Problem
Semiconductor devices face challenges in handling large volumes of data efficiently, requiring fast processing times and low power consumption, especially in mobile devices with high-resolution image and sound applications, and existing NAND flash memories experience increased power consumption and long rewrite times.
Innovation Solution
A semiconductor device with a novel structure comprising memory modules that include first and second memory cells, selection transistors, and wirings, utilizing transistors with metal oxide semiconductor layers and backgates to achieve fast data rewriting and low power consumption, with data being rewritten through multiple pathways to minimize power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory is used to store large volumes of data, then memory capacity is improved, but power consumption increases and rewrite time increases
Solution Approach 1:
The patent divides the memory system into multiple memory cells (first memory cell and second memory cell) with separate memory nodes (first memory node and second memory node). Each memory cell can be independently controlled through selection transistors, allowing selective rewriting of only the required memory node rather than rewriting all data, thus reducing power consumption while maintaining large memory capacity
Solution Approach 2:
The patent implements different transistor structures (rewrite transistors with metal oxide semiconductor layers and backgates) specifically for rewriting operations in localized regions. These transistors are positioned at specific locations (first and second ends of memory cells) to enable low-power rewriting of selected memory nodes without affecting other regions, achieving local optimization of power consumption
2Quantity of substance
If NAND flash memory is used to store large volumes of data, then memory capacity is improved, but rewrite time increases
Solution Approach 1:
The patent segments the memory array into multiple independently controllable memory cells with separate selection transistors. This allows parallel or selective rewriting of specific memory nodes (first memory node or second memory node) without affecting others, significantly reducing the time required to rewrite data in large-capacity memory systems
Solution Approach 2:
The patent uses selection transistors to pre-select which memory node (first or second) needs to be rewritten before the actual rewriting operation begins. This preliminary selection mechanism enables direct access to the target memory node without scanning or accessing other memory cells, thereby reducing rewrite time in large-capacity memory
3Use of energy by moving object
If power gating technique is used to reduce power consumption, then energy efficiency is improved, but data must be saved and processing time increases
Solution Approach 1:
The patent extracts the rewriting function from the general memory access path and creates a dedicated rewriting path using selection transistors and metal oxide semiconductor layer transistors. This separate rewriting mechanism allows data to be rewritten without requiring full power gating cycles, enabling power reduction while maintaining fast processing speed and avoiding data save delays
4Use of energy by moving object
If transistors with metal oxide semiconductor layers and backgates are used, then off-state current is reduced and power consumption is lowered, but device complexity increases
Solution Approach 1:
The patent applies the complex metal oxide semiconductor layer transistor structure with backgate only in specific locations where rewriting operations occur (selection transistors at first and second ends of memory cells). Other transistors in the memory system can use simpler structures, achieving power reduction at critical points without unnecessarily increasing complexity throughout the entire device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables fast data rewriting with reduced power consumption by using transistors with low off-state current and metal oxide semiconductor layers, allowing for efficient data handling and retention in semiconductor devices.
Implementation Method 1
transistors with metal oxide semiconductor layers and backgates to achieve fast data rewriting and low power consumption
Data Source
AI summary
An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL1. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBL1 through the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL1. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL1. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL1.