Memory Device Row-Address Precharging for Power-Gating

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Solution Overview

Problem

Memory devices face increased power consumption due to undetermined row addresses, which prevent the application of power-gating mechanisms, leading to inefficiencies in power management.

Innovation Solution

Implementing a precharging method for decoded row addresses in specific modes of the memory device, such as self-refresh and precharge power-down modes, to ensure power-gating can be applied, reducing off-current and overall power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If power-gating mechanism is applied to reduce power consumption, then power consumption is reduced, but it cannot be applied when row address is in undetermined state

Engineering Contradiction:
Improvepower consumptionVSAvoidrow address determination
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent applies preliminary action by precharging the row address signal to a known state (logic high or logic low) before the row address is fully determined or before power-gating is activated. This ensures that when power-gating is applied, the row address is already in a known state, preventing undetermined state issues while enabling power consumption reduction.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies preliminary anti-action by using a precharge circuit to counteract the potential undetermined state of the row address before power-gating is activated. The precharge circuit actively sets the row address to a known state, preventing the harmful effect of undetermined state from occurring in the first place.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If precharging is performed in all modes, then power-gating can be applied, but power consumption increases due to unnecessary precharging

Engineering Contradiction:
Improvepower-gating applicabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies dynamics by making the precharging operation conditional and adaptive based on the current operating mode. The precharge circuit is activated only in specific modes (e.g., self-refresh mode, precharge power-down mode) where it is necessary, and remains inactive in other modes where precharging would be unnecessary or harmful. This dynamic control optimizes the balance between ensuring power-gating applicability and minimizing power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies parameter changes by adjusting the precharging behavior based on different operating mode parameters. Different modes have different precharge requirements, and the system changes its precharging parameters (activation status, timing, duration) according to the current mode, thereby optimizing power consumption while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If precharging is performed in idle non-power-down mode, then power consumption is reduced, but it may not be necessary in all idle conditions

Engineering Contradiction:
Improvepower consumptionVSAvoidmode-specific optimization
Core Design Contradiction:
Loss of energyVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by implementing mode-specific precharging control. In idle non-power-down mode, the system dynamically determines whether precharging is necessary based on additional conditions (such as whether the row address is in undetermined state). This allows the system to adapt its behavior to specific idle conditions, performing precharging only when needed rather than universally in all idle modes.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12437797B2Memory device and precharging method thereof
Publication Date: 2025.10.07 SAMSUNG ELECTRONICS CO LTD
  • US12437797B2 patent drawing
  • US12437797B2 patent drawing
  • US12437797B2 patent drawing

AI summary

A memory device and a method of precharging a decoded address are provided. The memory device includes a memory cell array including a plurality of rows; a row decoder configured to select a row to be activated from among the plurality of rows based on a decoded row address; and an interface circuit configured to: generate the decoded row address based on decoding a plurality of bits of a row address, transfer the decoded row address to the row decoder, and in an idle non-power-down mode of the memory device, precharge the decoded row address that is transferred to the row decoder in response to a predetermined condition being satisfied.