Memory Structure Reducing Area via Row Column Diagonal Storage
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Solution Overview
Problem
Current memory structures used to store coding coefficients for video data occupy a large area due to the need for a large number of storage components.
Innovation Solution
A memory structure comprising a row storage circuit, a column storage circuit, and a diagonal storage circuit, where each storage component corresponds to a specific coordinate or diagonal line in the decoding unit, reducing the number of storage components and occupied area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional memory structure with sufficient storage components is used to store coding coefficients, then the reliability of data storage is improved, but the occupied area increases significantly
Solution Approach 1:
The memory structure is segmented into three specialized storage circuits: row storage circuit for storing coding coefficients by row, column storage circuit for storing by column, and diagonal storage circuit for storing by diagonal. Each circuit handles a specific dimension of data organization, reducing the total number of storage components needed while maintaining complete data availability for entropy decoding operations.
Solution Approach 2:
The patent introduces diagonal storage as an additional dimension beyond traditional row and column storage. By organizing coding coefficients along diagonal lines in addition to rows and columns, the system reduces redundancy in storage components while ensuring all necessary neighboring coefficients are accessible for decoding, thereby reducing occupied area without sacrificing reliability.
2Loss of information
If more storage components are used to ensure complete coding coefficient storage, then the loss of information is reduced, but the device complexity increases
Solution Approach 1:
The storage system is divided into three specialized circuits (row, column, diagonal) with distinct functions. Each circuit stores coding coefficients organized by a specific dimension, ensuring complete information is preserved while avoiding redundancy. This segmentation reduces device complexity by assigning specific roles to each storage component rather than using a monolithic storage structure.
Solution Approach 2:
Each storage circuit (row, column, diagonal) serves multiple purposes: storing coding coefficients, providing spatial organization for efficient access, and enabling complete information retrieval for entropy decoding. This multi-functionality reduces the need for additional dedicated components, thereby reducing overall device complexity while maintaining information completeness.
3Ease of manufacture
If traditional storage structures are used, then ease of manufacture is maintained, but the productivity of video decoding is reduced due to larger memory access requirements
Solution Approach 1:
The memory structure is segmented into three independent storage circuits that can be manufactured using standard semiconductor processes. Each circuit handles a specific dimension of data access, allowing for modular manufacturing while improving decoding productivity by reducing memory access time through organized data placement.
Solution Approach 2:
Coding coefficients are pre-organized in row, column, and diagonal storage circuits before decoding operations begin. This preliminary organization ensures that during entropy decoding, all necessary neighboring coefficients are already positioned for immediate access, eliminating the need for complex runtime memory management and improving video decoding speed without complicating manufacturing.
Data Source
AI summary
Disclosed are a memory structure, a storage method, an entropy decoding method, a chip, a device, and a storage medium. The memory structure includes: a row storage circuit including a plurality of row storage components in a number identical to a number of rows of a decoding unit, where the row storage components correspond one-to-one to ordinates of the decoding unit, and each row storage component is configured to store a coding coefficient under a corresponding ordinate, and an abscissa of the coding coefficient; a column storage circuit including a plurality of column storage components in a number identical to a number of columns of the decoding unit, where the column storage components correspond one-to-one to abscissas of the decoding unit, and each column storage component is configured to store a coding coefficient under a corresponding abscissa, and an ordinate of the stored coding coefficient; and diagonal storage components in a number equaling 1 subtracted from the sum of the number of rows and the number of columns of the decoding unit, where each diagonal storage component is configured to store a coding coefficient on a corresponding diagonal position line, and an abscissa or an ordinate of the stored coding coefficient. According to the disclosure, an occupied area of the memory structure is reduced.