Memory Device Row-Decoder Wiring for Compact Voltage Transfer
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Solution Overview
Problem
Existing memory devices face challenges in reducing size and failure, particularly in the disposition of coupling lines without increasing the device size, especially when global lines are present in the row decoder region.
Innovation Solution
The memory device incorporates a semiconductor structure with multiple bottom wiring layers and global lines positioned in specific tiers, allowing for the disposition of coupling lines without increasing the device size, and includes a row decoder with pass transistors that transfer operating voltages efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If global lines are disposed in the row decoder region, then operating voltages can be transferred to pass transistors, but the device size increases
Solution Approach 1:
The patent applies dimensionality change by moving global lines from the lateral plane to the vertical dimension through multiple bottom wiring layers. Global lines are disposed in specific bottom wiring layers (first or second tier) beneath the substrate level, allowing voltage transfer functionality to be maintained while eliminating occupation of lateral space in the row decoder region, thus resolving the contradiction between reliability and device size.
Solution Approach 2:
The patent implements nesting by embedding global lines within the multi-tiered bottom wiring layer structure. The global lines are nested in specific tiers (first or second bottom wiring layer) among multiple wiring layers, allowing them to be integrated into the existing vertical stack without expanding the lateral footprint, thereby maintaining voltage transfer capability while minimizing device area.
2Area of stationary object
If multiple bottom wiring layers are used, then coupling lines can be disposed without increasing device size, but the wiring layer complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the wiring structure into multiple distinct bottom wiring layers (first tier and second tier). Each layer serves specific functions: global lines are disposed in the first or second bottom wiring layer, while coupling lines are disposed in other bottom wiring layers. This segmentation allows efficient space utilization and reduces lateral device size while managing complexity through functional separation of wiring layers.
Solution Approach 2:
The patent implements local quality by assigning different wiring layers to different functional requirements. Specifically, global lines are placed in the first or second bottom wiring layer where they can efficiently reach pass transistors, while coupling lines are disposed in other bottom wiring layers. This localized optimization of wiring layer assignment minimizes overall device size while managing structural complexity through purpose-specific layer allocation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient voltage transfer and reduces signal delay, maintaining device performance while minimizing size and failure risks.
Implementation Method 1
a plurality of bottom wiring layers which are disposed between the substrate and the first bonding layer... configured to transfer operating voltages to the plurality of pass transistors
Data Source
AI summary
A memory device includes a first semiconductor structure including pass transistors defined in a row decoder region of a substrate, a first bonding layer including first bonding pads, and bottom wiring layers disposed between the substrate and the first bonding layer; a second semiconductor structure including a second bonding layer including second bonding pads bonded to the first bonding pads, a memory cell array, and a top wiring layer disposed between the second bonding layer and the memory cell array; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the bottom wiring layers include bottom wiring layers of a first tier and bottom wiring layers of a second tier disposed over the bottom wiring layers of the first tier, and the global lines are disposed in at least one of the bottom wiring layers of the first tier.