Semiconductor Memory Row Hammer Refresh Based on Access Patterns
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Solution Overview
Problem
Volatile memory devices like DRAM suffer from data loss due to leakage currents and adjacent cell degradation from frequent word-line transitions, necessitating frequent refresh operations that increase power consumption and chip size overhead, especially with increased capacity and non-uniform access patterns.
Innovation Solution
A semiconductor memory device with a row hammer management circuit that randomly selects row addresses based on uniform probability from an external controller, proportional to access counts, and performs hammer refresh operations on adjacent victim memory cells to mitigate row hammer effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to prevent data loss from leakage currents and row hammer effects, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The patent implements dynamic refresh rate adjustment by monitoring row access patterns and adapting the refresh frequency accordingly. The refresh control circuit receives row addresses from the memory controller and identifies frequently accessed rows, then performs refresh operations at different rates for different rows based on their access patterns, rather than using a uniform refresh rate for all rows.
Solution Approach 2:
The patent changes the refresh parameter (refresh rate) based on the access pattern of memory rows. The system monitors the number of times each row is accessed and adjusts the refresh interval dynamically, increasing refresh frequency for heavily accessed rows and decreasing it for lightly accessed rows, thereby optimizing the balance between data integrity and power consumption.
2Reliability
If uniform refresh rate is applied to all memory rows, then data integrity is maintained across the entire array, but power consumption increases due to unnecessary refresh operations on lightly accessed rows
Solution Approach 1:
The patent applies different refresh rates to different memory rows based on their local access patterns. The refresh control circuit processes row addresses individually or in groups and determines the refresh frequency for each row based on its specific access history, rather than applying a global uniform refresh rate to the entire memory array.
Solution Approach 2:
The system dynamically adjusts the refresh rate for each memory row based on real-time or near-real-time access pattern analysis. The refresh control circuit continuously monitors row access frequencies and adapts the refresh operations accordingly, making the refresh strategy dynamic rather than static.
3Productivity
If the memory device monitors and tracks access patterns for all rows, then optimized refresh operations can be performed, but device complexity increases
Solution Approach 1:
The patent utilizes the existing row address decoding and control logic in the memory device to also perform access pattern monitoring and refresh rate determination. The refresh control circuit leverages existing infrastructure (address latches, decoders, and control logic) to identify frequently accessed rows, rather than requiring completely separate monitoring circuits for each row.
Solution Approach 2:
The memory device uses its own internal row address information and control logic to monitor access patterns and determine refresh rates, without requiring external assistance or additional complex monitoring systems. The refresh control circuit processes row addresses that are already being generated and used for normal memory operations.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.