Memory Section Selection for Built-In Self-Test
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Solution Overview
Problem
Existing memory built-in self-test (MBIST) techniques require long test times when testing entire memory devices, which is unacceptable for in-the-field testing, leading to potential interruptions and reduced reliability due to extended periods of non-functionality.
Innovation Solution
Implementing a memory section selection method that allows for testing of specific sections of the memory device, enabling faster test times and increased flexibility by allowing all sections to be tested during manufacturing and subsets during in-the-field testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If entire memory device is tested using MBIST, then manufacturing precision is improved, but test time increases significantly
Solution Approach 1:
The memory device is divided into multiple testable sections, allowing the MBIST to be performed on only the necessary sections rather than the entire memory device. This segmentation enables faster testing while maintaining manufacturing precision for the tested portions.
2Reliability
If MBIST is performed during in-the-field testing, then reliability is improved, but device functionality is interrupted for extended periods
Solution Approach 1:
By segmenting the memory into testable sections, the MBIST can be performed on only the necessary portions during in-the-field testing, significantly reducing the duration of functionality interruption while maintaining reliability through comprehensive error detection in the tested sections.
Solution Approach 2:
Instead of testing the entire memory device during in-the-field operations, only the necessary sections are tested using MBIST. This partial action approach maintains sufficient reliability for the tested portions while minimizing operational interruptions.
3Manufacturing precision
If all memory sections are tested during manufacturing, then manufacturing precision is improved, but productivity decreases due to extended test times
Solution Approach 1:
The memory device is segmented into multiple testable sections, enabling the manufacturing process to test only the necessary sections. This increases manufacturing precision for the tested portions while improving overall productivity by reducing the time required to test the entire device.
Data Source
AI summary
Implementations described herein relate to memory section selection for a memory built-in self-test. A memory device may read a first set of bits stored in a test control mode register. The memory device may identify a test mode, for performing a memory built-in self-test, based on the first set of bits. The memory device may read a second set of bits stored in a section identifier mode register. The memory device may identify one or more memory sections of the memory device, for which the memory built-in self-test is to be performed, based on the second set of bits. The one or more memory sections may be a subset of a plurality of memory sections into which the memory device is divided. The memory device may perform the memory built-in self-test for the one or more memory sections of the memory device based on the test mode.