Semiconductor Memory Device Segmentation for Yield and Density
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Solution Overview
Problem
Stacked-type semiconductor memory devices face challenges in achieving compatibility between high integration and high yield, particularly in managing the write characteristics of memory cells to optimize data storage density and efficiency.
Innovation Solution
The semiconductor memory device classifies memory cells into two groups based on their write characteristics, operating cells with insufficient write characteristics in 8-value mode to improve yield and those with favorable characteristics in 16-value mode to enhance recording density, using a control circuit to manage data conversion between the two modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If all memory cells operate in 16-value mode to maximize recording density, then recording density is improved, but yield deteriorates due to insufficient write characteristics in some cells
Solution Approach 1:
The memory cells are segmented into two distinct groups: first group cells operate in 16-value mode for maximum recording density, while second group cells operate in 8-value mode for reliable operation. This segmentation allows each group to be optimized independently according to its write characteristics, resolving the contradiction between maximizing recording density and maintaining yield.
Solution Approach 2:
Different operational modes (16-value vs 8-value) are assigned to different groups of memory cells based on their local write characteristics. Cells with favorable write characteristics locally operate in 16-value mode, while cells with insufficient write characteristics locally operate in 8-value mode, allowing each cell to operate at its optimal performance level.
2Reliability
If all memory cells operate in 8-value mode to ensure sufficient write characteristics, then yield is improved, but recording density deteriorates
Solution Approach 1:
The memory array is divided into two operational groups, allowing the system to achieve high yield through the 8-value mode group while simultaneously achieving high recording density through the 16-value mode group. The overall system benefits from both approaches without compromising either yield or recording density.
Solution Approach 2:
The operational parameter (number of values per cell) is changed based on the write characteristics of each memory cell group. By dynamically adjusting the operational mode parameter between 8-value and 16-value, the system optimizes both yield and recording density according to the actual performance of each cell group.
3Quantity of substance
If memory cells with insufficient write characteristics are operated in 16-value mode, then recording density is maximized, but write time increases and manufacturing costs increase
Solution Approach 1:
By segmenting memory cells into two groups based on write characteristics, the system avoids forcing cells with insufficient write characteristics into 16-value mode. Instead, these cells operate in 8-value mode with shorter write times, while only cells with favorable characteristics operate in 16-value mode, thus reducing overall write time and manufacturing costs.
Solution Approach 2:
The system applies partial 16-value operation only to cells that can handle it, rather than attempting full 16-value operation across all cells. This partial approach to high-density operation avoids the excessive write times and costs that would result from forcing all cells into 16-value mode.
Data Source
AI summary
A semiconductor memory device includes a substrate, electrode films provided on a first direction side of the substrate and arranged with spacing from each other along the first direction, semiconductor members extending in the first direction, a charge storage member provided between each of the electrode films and each of the semiconductor members, and a control circuit. Memory cells are formed in crossing portions of the electrode films and the semiconductor members. The control circuit classifies the memory cells into a first group and a second group. The control circuit performs writing, reading, and erasing of n-value data (n being an integer of two or more) on the memory cell of the first group. The control circuit performs writing, reading, and erasing of m-value data (m being an integer larger than n) on the memory cell of the second group.