Semiconductor Memory Device Segmented ECC and Pass Page Repair
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Solution Overview
Problem
Semiconductor memory devices face a tradeoff between memory density and reliability, where increased memory density often leads to reduced reliability due to bad cells, necessitating a solution that maintains reliability without requiring redundant cells for error correction.
Innovation Solution
A semiconductor memory device with a memory cell array divided into two regions, where the first region provides consecutive address space by correcting single-bit errors using an ECC circuit and the second region is reserved for repairing failed pages, eliminating the need for redundant cells by using a pass page from the second region to replace failed pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density is increased, then memory capacity is improved, but reliability deteriorates due to increased bad cells
Solution Approach 1:
The memory cell array is divided into a first memory region for normal data storage and a second memory region for storing pass pages that can replace failed pages. This segmentation allows the system to handle bad cells without reducing overall memory density, as the second region acts as a dedicated repair pool that doesn't interfere with the primary storage capacity.
Solution Approach 2:
The patent creates copies of good pages (pass pages) in the second memory region that can serve as replacements for failed pages in the first memory region. Instead of using traditional redundant cells that require complex mapping, the system copies entire functional pages that can directly replace failed pages, simplifying the repair mechanism while maintaining high density.
2Reliability
If redundant cells are added for error correction, then reliability is improved, but memory density deteriorates
Solution Approach 1:
The memory is segmented into functional regions where the second memory region is specifically designated for storing replacement pages. This segmentation allows the system to provide reliability through dedicated repair pages without sacrificing overall memory density, as the replacement pages are organized in a separate region that can be efficiently managed.
Solution Approach 2:
The patent changes the organizational parameter of redundancy from traditional bit-level redundant cells to page-level replacement pages. By storing entire pass pages in the second memory region rather than individual redundant bits, the system achieves reliable error correction while minimizing the impact on memory density through more efficient use of redundant space.
3Reliability
If traditional ECC with redundant cells is used, then single-bit errors are corrected, but device complexity increases
Solution Approach 1:
The memory cell array is divided into a first memory region for normal operation and a second memory region for storing pass pages. This segmentation simplifies the error handling process by providing a dedicated pool of replacement pages, reducing the complexity of address mapping and repair logic compared to traditional redundant cell structures.
Solution Approach 2:
The patent uses copied pass pages in the second memory region as direct replacements for failed pages, eliminating the need for complex redundant cell mapping and decoding circuits. This copying approach simplifies the device structure by using entire functional pages as replacements rather than requiring complex reconstruction from redundant bits.
4Reliability
If failed pages are replaced with pass pages from the second region, then reliability is improved, but address space continuity may be affected
Solution Approach 1:
The second memory region serves multiple functions: it stores pass pages for replacing failed pages in the first region, and can also provide consecutive address space when needed. This multi-functionality allows the system to maintain both reliability through page replacement and address space continuity, as the second region can be accessed directly for sequential addressing operations.
Solution Approach 2:
The system dynamically manages the address space by allowing the second memory region to serve different purposes based on operational needs. When failed page replacement is needed, the second region provides pass pages; when consecutive addressing is needed, the second region can be accessed sequentially. This dynamic flexibility resolves the contradiction between reliability and address space continuity.
Data Source
AI summary
The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.