3D Non-Volatile Memory Selection Gate Threshold Control

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Solution Overview

Problem

Three-dimensional memory devices face challenges in accurately selecting memory cells due to variations in threshold voltages and potential transmission delays across different regions of the selection gate layers, leading to potential errors in data writing.

Innovation Solution

The semiconductor memory device incorporates a stacked body with conductive layers and a selection gate layer, where the threshold voltage of certain selection transistors is adjusted based on their regions to compensate for transmission delays, ensuring uniform potential application and minimizing errors during data writing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a stacked body with multiple conductive layers is used to increase memory capacity, then storage density is improved, but potential transmission delays across different regions of the selection gate layers cause errors in data writing

Engineering Contradiction:

Improvememory capacityVSAvoiddata writing accuracy

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The selection gate layer is divided into multiple regions with different threshold voltages. Specifically, a first region has a first threshold voltage and a second region has a second threshold voltage that is higher than the first threshold voltage. This local differentiation compensates for transmission delays in different regions, ensuring accurate data writing while maintaining high storage density through the stacked three-dimensional structure.

Inventive Principle:

Principle #3Local quality

2Reliability

If the selection gate layer is divided into multiple regions with different threshold voltages, then data writing accuracy is improved, but device complexity increases

Engineering Contradiction:

Improvedata writing accuracyVSAvoidselection gate layer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The selection gate layer is segmented into multiple regions along the stacking direction, with each region having a distinct threshold voltage. The first region contains a first selection transistor with a first threshold voltage, while the second region contains a second selection transistor with a second threshold voltage. This segmentation approach systematically manages the complexity by creating clearly defined regions with specific functions, making the device easier to control and manufacture despite the increased number of regions.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10593691B2Three-dimensional non-volatile memory device with cut off time control

Publication Date: 2020.03.17 KIOXIA CORP

AI summary

According to one embodiment, selection gates include an extract portion, a first portion, and a second portion. A predetermined potential is transmitted from the extract portion to the first portion. The predetermined potential is transmitted from the extract portion to the second portion with a delayed time to the first portion. A threshold voltage of a first selection transistor is different from a threshold voltage of a second selection transistor. The first selection transistor includes a semiconductor body disposed in the first portion as a channel. The second selection transistor includes the semiconductor body disposed in the second portion as a channel.