Nonvolatile Memory Device Selective Erase Verification Latch
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Solution Overview
Problem
Current nonvolatile memory devices face inefficiencies in erasing operations, particularly in verifying the erase status of memory cells, which can lead to data integrity issues and prolonged operation times due to the need to apply erase verify voltage to all word lines, resulting in reduced accuracy and increased time.
Innovation Solution
A method and device that store partial addresses of word lines in a latch, allowing for selective erase verification on a per-word line basis, resuming erase verification from failed word lines and adjusting erase voltage, thereby reducing RC loading and improving erase verification accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase verification is performed on all word lines, then data integrity is ensured, but operation time increases
Solution Approach 1:
The patent segments the erase verification process by dividing word lines into two groups: those stored in the latch (requiring verification) and those not stored in the latch (exempt from verification). This segmentation allows the system to focus verification resources only on critical word lines, reducing overall verification time while maintaining data integrity for the most important memory regions.
Solution Approach 2:
The patent applies different verification quality levels to different word lines. Word lines stored in the latch receive full verification attention, while other word lines receive reduced or no verification. This local quality approach ensures that critical data regions maintain high integrity while non-critical regions consume minimal verification resources, resolving the time-integrity tradeoff.
2Measurement precision
If erase verification is performed on all word lines, then comprehensive checking is achieved, but RC loading increases
Solution Approach 1:
The patent extracts the verification burden from the entire set of word lines and concentrates it only on those word lines whose addresses are stored in the latch. By taking out the verification requirement from non-latch word lines, the system reduces RC loading and circuit complexity while maintaining sufficient verification accuracy for critical regions.
3Productivity
If partial word line addresses are stored in latch, then erase verification time is reduced, but verification coverage decreases
Solution Approach 1:
The patent uses preliminary action by pre-storing the addresses of critical word lines in the latch before the erase operation begins. This preliminary selection of which word lines require verification allows the system to achieve both high speed (by limiting verification to pre-selected lines) and adequate coverage (by ensuring critical lines are pre-identified and stored in the latch).
Data Source
AI summary
A method of operating a non-volatile memory device includes storing one or more addresses of word lines (WLs), but not the entire addresses of the WLs, into a latch, the WLs disposed between a string selection line (SSL) and a ground selection line (GSL), selecting a first WL from the latch, performing an erasing operation on memory cells associated with the string selection line (SSL), the memory cells associated with the SSL constituting a memory block, and verifying the erasing operation on memory cells associated with the selected first WL.