Memory Device Selective Erase Voltage Control
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Solution Overview
Problem
Existing memory devices face challenges in efficiently performing erase operations without inadvertently erasing non-target strings, which can lead to unnecessary voltage application and threshold voltage lowering in completely erased cells.
Innovation Solution
A memory device design that includes strings connected between a bit line and a source line, with a peripheral circuit capable of applying different erase voltages and select voltages to target and non-target strings during an erase operation, preventing non-target strings from being erased by floating their select lines during voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a memory device performs an erase operation on all strings simultaneously by applying erase voltage to bit lines and source lines, then the erase operation can be performed efficiently and simply, but non-target strings will be inadvertently erased causing unnecessary voltage application and threshold voltage lowering
Solution Approach 1:
The patent segments the erase operation into two distinct phases: a first erase operation on target strings and a second erase operation on non-target strings. By dividing the simultaneous erase operation into sequential operations with different voltage levels, the patent prevents unnecessary voltage application to completely erased cells while maintaining erase efficiency. The first section applies a first erase voltage to target strings, and the second section applies a second erase voltage to non-target strings, eliminating the need to apply high erase voltage to all strings simultaneously.
2Reliability
If the memory device applies high erase voltage to all strings to ensure complete erasure, then all memory cells are erased, but completely erased cells experience unnecessary threshold voltage lowering
Solution Approach 1:
The patent applies different erase voltages to different groups of strings based on their erasure status. Target strings receive the first erase voltage for complete erasure, while non-target strings receive the second erase voltage only after the first erase operation. This localized differentiation ensures that high voltage is applied only where needed for complete erasure, preventing unnecessary threshold voltage lowering in completely erased cells while maintaining reliable erasure of strings that require it.
3Device complexity
If the memory device uses a simple erase operation without selective voltage control, then the circuit design is simpler, but it cannot prevent inadvertent erasure of non-target strings
Solution Approach 1:
The patent introduces dynamic voltage control where the erase voltage applied to bit lines and source lines changes based on the operational phase. During the first erase operation, a first erase voltage is applied to target strings, and during the second erase operation, a second erase voltage is applied to non-target strings. This dynamic adjustment of voltage levels based on string selection enables precise selective erasure while maintaining relatively simple circuit design, as the same bit line and source line structures are used with different voltage applications.
Data Source
AI summary
A memory device includes strings and a peripheral circuit. The strings are connected between a bit line and a source line. The peripheral circuit is configured to perform an erase operation on a first string among the strings by applying an erase voltage to at least one of the bit line and the source line and configured to control a second string among the strings to be prohibited from being erased during the erase operation.