Memory Self-Test Circuit Reduces ATE Dependency
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Solution Overview
Problem
The existing semiconductor testing methods face challenges with high test costs, long test cycles, and limited test speed due to the use of Automatic Test Equipment (ATE) for testing memories, particularly as the size of semiconductor processes decreases and IC complexity increases, leading to potential defects and increased costs for probe cards and high-speed testing.
Innovation Solution
A method and device utilizing a built-in self-test circuit (BIST) with a First-In-First-Out (FIFO) queue to buffer command signals, generate a test clock signal with a different phase than the ATE, and parallel testing of multiple memory dies using a control die with limited command pins, allowing for efficient data transfer and reduced peripheral pin usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ATE is used to test DRAM through Direct Access Pads, then testing can be performed, but as bit width increases, one touch down cannot test a whole wafer and high-speed machines are required which increase test cost
Solution Approach 1:
The patent implements a built-in self-test circuit (BIST) within the storage device that can autonomously perform testing functions. The BIST circuit generates test patterns, controls test sequences, and evaluates test results internally, reducing dependency on external ATE equipment and enabling cost-effective high-speed testing without requiring expensive high-speed ATE machines
Solution Approach 2:
The control die integrates a multi-functional BIST circuit that can test multiple memory dies simultaneously through a single touch down. The circuit supports various test modes and can adapt to different memory configurations, making the testing system universally applicable across different wafer layouts and memory types while reducing the need for multiple specialized test setups
2Reliability
If ATE is used for memory testing, then testing can be performed, but test cycle time is long and test cost is high
Solution Approach 1:
The BIST circuit performs preliminary testing actions by generating test patterns and executing test sequences internally before final validation. This preliminary self-testing capability allows for rapid initial screening of memory dies, significantly reducing the overall test cycle time while maintaining comprehensive defect detection coverage
Solution Approach 2:
The patent enables continuous testing operations by implementing a self-sustaining BIST circuit that can autonomously execute test sequences without interruption. The circuit maintains continuous test operations across multiple memory dies simultaneously, eliminating idle time between tests and maximizing productivity without compromising test thoroughness
3Productivity
If a large number of DA pads are provided on control die for ATE testing, then testing capability is improved, but probe card preparation cost increases
Solution Approach 1:
The patent merges multiple testing functions into a single integrated BIST circuit on the control die. By combining pattern generation, test control, and result evaluation functions into one self-contained unit, the system achieves comprehensive testing capability while requiring minimal external pad connections, thereby dramatically reducing probe card complexity and preparation costs
Data Source
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AI summary
A method and a device for testing a memory, an electronic device, and a computer-readable storage medium are provided. The method includes: obtaining a test instruction; generating, in response to the test instruction, a test clock signal, a to-be-tested address and to-be-tested data; determining a to-be-tested memory from memories of a storage device, the storage device including a self-test circuit; writing the to-be-tested data into a storage unit corresponding to a to-be-tested address of the to-be-tested memory; reading output data from the storage unit corresponding to the to-be-tested address of the to-be-tested memory; and comparing the to-be-tested data with the output data corresponding to the to-be-tested address to obtain a test result of the to-be-tested memory. The self-test circuit disposed in the storage device is configured to implement a memory test process. Thus, the dependency on automatic test equipment is reduced, thereby improving test speed and reducing test cost.