Memory Data Path Self-Test With Multi-Speed Test Clocks
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in testing the data path between IO pads and buffer memory due to the need for high-speed test clocks that are not suitable for other test modes, such as setting trim values.
Innovation Solution
Implementing built-in self-test circuitry with multiple test modes that utilize a divided test clock signal frequency based on the selected test, allowing for high-speed data path testing and stress or trim mode operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-speed test clock is used for data path testing, then testing speed and productivity are improved, but the clock signal cannot be used for other test modes such as trim mode operations
Solution Approach 1:
The test clock signal is segmented into multiple frequency versions using divide-by-N circuitry. A single high-speed test clock is divided into different frequency clocks (e.g., divided by 1, 2, 4, 8) to support various test modes including high-speed data path testing and lower-speed trim mode operations, allowing one clock source to serve multiple functions.
Solution Approach 2:
The test clock generation circuitry is designed to be universal by providing multiple frequency outputs from a single high-speed clock source. The divide-by-N circuitry enables the same clock infrastructure to support both high-speed testing and lower-speed operations across different test modes, eliminating the need for separate clock sources.
2Device complexity
If a single test clock is used for all test modes, then device complexity is reduced, but testing precision and reliability deteriorate due to insufficient clock speed for high-speed data path testing
Solution Approach 1:
The clock frequency is made dynamic and adjustable based on the test mode being performed. The divide-by-N circuitry allows the system to switch between different clock frequencies dynamically, using high-speed clocks for data path testing when needed and lower speeds for other modes, optimizing both reliability and resource utilization.
3Productivity
If high-speed test clock is used continuously, then productivity is improved, but energy consumption increases and device heating occurs
Solution Approach 1:
The high-speed test clock is activated periodically only when high-speed data path testing is required, rather than running continuously. The divide-by-N circuitry enables switching between high-speed and lower-speed modes as needed, reducing overall energy consumption while maintaining high productivity when performance testing is performed.
Data Source
AI summary
Built-in self-test circuitry of a non-volatile memory device is presented for testing the data path between the input/output (IO) pads of a memory chip and the buffer memory used to store data to be written into or read out of a memory array. One set of tests on the data path can be high speed data path tests to determine whether the memory device can handle the transfer speed of user data transfer to and from the memory device. However, this requires data path testing based on a high speed test clock which may not be suitable for other test modes, such as setting trim values. To address this issue, the following presents testing techniques and circuitry for data path testing having multiple modes, in which the frequency of the test clock signal is divided by differing amounts depending on the test selected.