Programmable Re-mapper for Memory Self-Test Address Translation
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Solution Overview
Problem
Existing self-test systems for memory defects in data processing systems face challenges due to varying memory configurations and indexing methods, leading to compromised test accuracy and inability to target specific memory cell physical access patterns effectively.
Innovation Solution
A programmable re-mapper is introduced to re-map generated memory addresses based on programmable mapping selection data, ensuring that memory cells are accessed according to the intended physical access pattern, regardless of the memory system's indexing implementation, allowing for flexible and accurate self-testing across different memory configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a generic self-test system is designed to accommodate various memory configurations, then adaptability improves, but test accuracy deteriorates because the system cannot reliably target specific physical access patterns across different implementations
Solution Approach 1:
A re-mapper component is introduced as an intermediary between the self-test controller and the memory array. The re-mapper receives generated memory addresses from the controller and translates them into the correct physical addresses according to the specific memory implementation's addressing scheme. This mediator enables the same self-test algorithm to accurately target physical memory cells across different memory configurations without requiring changes to the test controller or algorithms.
2Ease of manufacture
If memory addresses are generated according to a standard addressing scheme, then self-test algorithm implementation is simplified, but the ability to target specific physical memory cells deteriorates when memory implementations use different addressing schemes
Solution Approach 1:
The address generation system is made dynamic by incorporating a re-mapper that can adaptively translate addresses based on the specific memory implementation. Instead of using a fixed addressing scheme, the system dynamically adjusts the address mapping according to the memory's physical configuration, row-column organization, and addressing scheme. This allows the same self-test controller to work with different memory implementations while maintaining precise physical cell targeting.
3Measurement precision
If hardware changes are made to accommodate different memory mappings, then test accuracy for specific physical patterns is maintained, but device complexity increases
Solution Approach 1:
Instead of changing the physical hardware addressing circuitry for different memory implementations, the patent creates a software-based copy of the addressing logic through the re-mapper. The re-mapper implements different address translation functions through programmable logic or configuration, allowing the same hardware to simulate different addressing schemes. This avoids the need for complex hardware changes while maintaining test accuracy across various memory configurations.
Data Source
AI summary
A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.