Memory Sense Amplifier Circuit for Fast Nonvolatile Readout
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Solution Overview
Problem
Existing semiconductor circuits face challenges in performing high-speed data reading operations, particularly in nonvolatile memory circuits where large volumes of data need to be read out quickly.
Innovation Solution
The semiconductor circuit incorporates a configuration with first and second memory cells, signal lines, a sense amplifier, and switches, utilizing a latch circuit and transistors to invert voltages and apply control voltages, enabling efficient coupling and reading operations while preventing resistance state changes in memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional memory circuit configuration is used, then the circuit structure is simple, but the data reading speed is slow and cannot handle large volumes of data quickly
Solution Approach 1:
The memory circuit is segmented into multiple independent memory cells (first memory cell, second memory cell) with separate signal lines and sensing paths. Each memory cell can be accessed and read independently through its own bit line and sense amplifier, enabling parallel data reading operations that significantly improve reading speed while maintaining manageable circuit complexity through modular design
Solution Approach 2:
The patent introduces a third dimension to the sensing mechanism by adding a control voltage applied to the third transistor that couples to the sources of the first and second transistors. This additional control dimension enables dynamic adjustment of the sensing operation, allowing for high-speed reading by optimizing the coupling strength between the memory cells and sense amplifiers without increasing the basic two-dimensional circuit layout complexity
2Speed
If high current is applied to read data quickly, then reading speed improves, but the resistance state of memory elements changes unintentionally
Solution Approach 1:
The sense amplifier implements a feedback mechanism where the voltage at the first node is fed back through the latch circuit to the second node, and vice versa. This feedback allows the circuit to detect the resistance state of memory elements by measuring voltage differences caused by current flow, enabling high-speed reading through amplified voltage signals rather than requiring high current that would alter the memory element resistance states
Solution Approach 2:
The patent introduces voltage as an intermediary quantity to mediate between the memory element resistance state and the read output. Instead of directly measuring current through the memory elements (which would require high current), the circuit converts resistance information into voltage differences at the sense amplifier nodes, then amplifies and latches these voltage signals for high-speed reading without disturbing the original resistance states
Data Source
AI summary
A semiconductor circuit according to the present disclosure includes first and second memory cells, first and second signal lines, a sense amplifier, a first switch, and a second switch. The sense amplifier includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit is configured to apply, to a second node, a voltage inverted with respect to a voltage at a first node and apply, to the first node, a voltage inverted with respect to a voltage at the second node. The first transistor includes a source, and includes a gate and a drain that are coupled to the first node. The second transistor includes a source, and includes a gate and a drain that are coupled to the second node. The third transistor includes a source, a gate to which a control voltage is applicable, and a drain coupled to the source of the first transistor, the source of the second transistor, or both. The first switch is configured to couple the first signal line and the first node to each other. The second switch is configured to couple the second signal line and the second node to each other.