Semiconductor Memory Sense Amplifier Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As NAND flash memory cells become smaller, the increased circuit area of the sense amplifier unit leads to longer bus wiring, resulting in higher power consumption due to repeated current passing through the wiring.
Innovation Solution
The semiconductor memory device incorporates a configuration with multiple sense amplifier circuits and data latch circuits connected via local and global buses, optimizing data transfer paths to reduce the length and capacity of data buses, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased by making cells smaller, then storage capacity is improved, but the circuit area of peripheral circuits increases leading to longer bus wiring and higher power consumption
Solution Approach 1:
The patent divides the sense amplifier unit into multiple circuit groups (first circuit group, second circuit group, etc.) arranged in a column direction. Each group contains sense amplifier circuits and data latch circuits that can operate independently. This segmentation allows data to be processed in parallel across multiple groups, reducing the need for long bus wiring to connect all sense amplifiers to a single data latch unit, thereby reducing power consumption in the bus wiring.
Solution Approach 2:
The patent introduces a row direction in addition to the column direction, creating a two-dimensional arrangement of circuit groups. Sense amplifier circuits are arranged both in rows and columns, with data latch circuits positioned at specific intersections. This dimensional expansion allows for more efficient data routing and reduces the average distance data must travel through bus wiring, reducing power consumption.
2Quantity of substance
If the circuit area of the sense amplifier unit is increased to support more memory cells, then storage capacity is improved, but the length of bus wiring increases resulting in higher power consumption
Solution Approach 1:
The patent segments the sense amplifier unit into multiple circuit groups distributed across the memory cell array. Each circuit group processes data locally before transferring results through shorter bus connections. This segmentation reduces the maximum distance any single data signal must travel through bus wiring compared to a centralized architecture, thereby reducing overall bus wiring length and associated power consumption.
Solution Approach 2:
The patent enables dynamic selection of which circuit group processes which bit line data through control signals. This dynamic allocation allows the system to optimize data paths based on operational requirements, potentially routing data through shorter bus wiring paths when possible, thereby reducing power consumption during data read operations.
Data Source
AI summary
A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group including one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.