Memory Device Separate Row Column Control Channels
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Solution Overview
Problem
Conventional memory devices have limitations in operating multiple memory banks simultaneously due to a single channel for receiving command and address signals, which slows down operation speed and increases package size.
Innovation Solution
The memory device incorporates separate channels for receiving row and column control signals, allowing for simultaneous operation of multiple bank groups and reducing the number of input pads required, enabling faster operation and smaller size through sequential signal reception synchronized with clock edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single channel is used for receiving command and address signals, then the device structure is simpler, but the operation speed is limited and multiple memory banks cannot operate simultaneously
Solution Approach 1:
The patent divides the signal receiving function into separate channels: a first channel for receiving row control signals and a second channel for receiving column control signals. This segmentation allows independent signal reception paths, enabling multiple memory banks to operate simultaneously without signal interference, thereby improving operation speed while maintaining manageable structural complexity through functional decomposition.
2Loss of time
If multiple input pads are used to receive all control signals simultaneously, then all signals can be received at once, but the package size increases
Solution Approach 1:
The patent implements preliminary action by receiving row control signals and column control signals in sequential clock cycles rather than requiring all signals to be received simultaneously. The first channel receives row control signals during one clock cycle, and the second channel receives column control signals during the same or subsequent clock cycles. This sequential reception approach reduces the number of input pads needed while maintaining fast operation speed, thereby reducing package size without sacrificing time efficiency.
3Reliability
If command and address signals are received at the first rising edge of the clock, then signal reception is synchronized, but both input units must have multiple input pads which lowers operation speed
Solution Approach 1:
The patent segments the signal reception process into two independent channels that operate in parallel. The first channel receives row control signals at the first rising edge of the clock, while the second channel receives column control signals at the same or subsequent rising edges. This segmentation allows synchronized signal reception without requiring both input units to have multiple input pads, thereby maintaining reliability while improving operation speed.
Data Source
AI summary
A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.