Memory Controller SG Scan Distribution Across Erase Cycles
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Solution Overview
Problem
Conventional memory sub-systems face inefficiencies in garbage collection and erase operations due to the substantial time required for performing select gate (SG) scan operations on memory components nearing the end of their life, which slows down the overall operation and increases the risk of errors.
Innovation Solution
A memory controller divides memory operations across multiple program-erase cycles, performing SG scan operations on alternating groups of memory regions within each cycle to expedite garbage collection and erase processes, thereby improving efficiency and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SG scan operations are performed on all memory regions during each erase cycle, then reliability testing is thorough, but garbage collection and erase operations become slow
Solution Approach 1:
The patent divides memory regions into multiple groups and performs SG scan operations on different groups in alternating erase cycles. This segmentation allows the system to maintain thorough reliability testing while avoiding the performance penalty of testing all regions in every cycle, as only a subset of groups is tested during each individual erase operation.
Solution Approach 2:
The patent implements periodic reliability testing by distributing SG scan operations across multiple erase cycles. Instead of performing comprehensive testing in every cycle, the system alternates between testing different groups of memory regions, ensuring that all regions are tested periodically over time while maintaining high erase operation speed in individual cycles.
2Reliability
If SG scan operations are performed on all memory regions during each erase cycle, then reliability is ensured, but the overall operation time increases
Solution Approach 1:
By segmenting memory regions into multiple groups and testing only a subset during each erase cycle, the patent reduces the time required for individual erase operations while ensuring that all regions are tested over a series of cycles. This segmentation strategy prevents any single operation from becoming time-consuming.
Solution Approach 2:
The patent employs periodic action by distributing comprehensive reliability testing across multiple erase cycles. Each individual cycle performs SG scan operations on a subset of groups, reducing per-cycle time, while the periodic repetition across cycles ensures complete coverage of all memory regions for thorough reliability assurance.
3Productivity
If SG scan operations are distributed across multiple erase cycles, then erase operations become faster, but the complexity of managing test groups increases
Solution Approach 1:
The patent manages complexity by clearly segmenting memory regions into distinct groups with systematic indexing. This structured segmentation provides a straightforward framework for tracking which groups have been tested and which remain, simplifying the management of test distributions across multiple cycles despite the increased operational speed.
Data Source
AI summary
The disclosure configures a memory sub-system controller to distribute memory operations across multiple program-erase (PE) cycles. The controller determines that an individual portion of a set of memory components satisfies a degradation criterion. The controller applies a memory operation on a first group of regions of a plurality of regions of the individual portion to test reliability of the first group of regions as part of performing a first PE cycle on the individual portion. The controller applies the memory operation on a second group of regions of the plurality of regions to test reliability of the second group of regions as part of performing a second PE cycle on the individual portion and selectively retires the individual portion based on results of testing the reliability of the first group of regions and the second group of regions across the first PE cycle and the second PE cycle.