Memory Architecture with Shared Bitlines for Lower Row-Cycle Delay
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Solution Overview
Problem
The high delay in memory systems, primarily caused by row cycle time (tRC) in large memory arrays, hinders the performance of computer systems.
Innovation Solution
A memory architecture with fine-grained storage blocks, shared global bitlines and wordlines, and signal amplification circuits to reduce parasitic capacitance and circuit drive time, allowing simultaneous read/write operations across multiple storage units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large memory array is used, then storage capacity is improved, but row cycle time delay increases
Solution Approach 1:
The memory array is divided into multiple storage blocks (first storage block, second storage block, etc.), each with its own local bitlines and local wordlines. This segmentation reduces the distance for data transmission within each block, thereby reducing row cycle time delay while maintaining overall storage capacity through the combination of multiple blocks.
Solution Approach 2:
Global bitlines and global wordlines serve as intermediary transmission lines that connect multiple storage blocks. The bitline switches and wordline switches act as mediators to control signal transmission between local lines and global lines, enabling efficient data access across the segmented memory structure without increasing delay.
2Ease of operation
If long-distance data transmission is performed on bitlines, then data access is enabled, but transmission delay increases
Solution Approach 1:
The bitline structure is segmented into local bitlines within each storage block and global bitlines for inter-block connection. This segmentation ensures that data transmission within a block occurs over short distances, minimizing transmission delay while global bitlines provide necessary connectivity across blocks.
Solution Approach 2:
The patent introduces a hierarchical dimension to bitline organization, transitioning from a single-level bitline structure to a two-level structure with local and global bitlines. This dimensional change allows data to be transmitted efficiently within local blocks while maintaining system-wide accessibility through global bitlines.
3Quantity of substance
If storage units are arranged in a large array, then storage capacity is improved, but circuit drive time increases
Solution Approach 1:
The memory array is segmented into multiple storage blocks, each with dedicated local wordlines and local bitlines. This segmentation reduces the length of wordlines and bitlines within each block, thereby reducing circuit drive time while the collective capacity of all blocks provides the required storage capacity.
Solution Approach 2:
Each storage block operates as an independent unit with its own control lines, allowing partial operations within blocks without requiring full array activation. This enables more granular control and reduces the drive time required for individual access operations while maintaining the ability to access any block in the larger array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture enhances read/write speeds and reduces costs by minimizing the length of local bitlines and wordlines, thereby improving memory performance and efficiency.
Implementation Method 1
a signal amplification circuit, the signal amplification circuit is configured to amplify electrical signals on the N global bitlines
Data Source
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Figure 2B
AI summary
A data reading/writing method, a memory, a storage apparatus, and a terminal are provided. The memory includes S storage blocks, N global bitlines, and a signal amplification circuit. Each of the S storage blocks is connected to the N global bitlines, the N global bitlines are connected to the signal amplification circuit, the signal amplification circuit is configured to amplify electrical signals on the N global bitlines, and each storage block includes N columns of storage units, N local bitlines, and N bitline switches. In each storage block, storage units in an ith column are connected to an ith local bitline, the ith local bitline is connected to an ith global bitline by using an ith bitline switch in the N bitline switches. A memory array is fine-grained, so that ith local bitlines in the S storage blocks can share one global bitline. This can shorten the local bitline, reduce parasitic capacitance caused by the local bitline, and reduce a delay of the memory.