Memory Signal Propagation Circuit With Feedback for Fast Switching
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Solution Overview
Problem
Current semiconductor memory devices face challenges in signal propagation efficiency, leading to signal loss due to manufacturing errors and attenuation, particularly in the switching of input signals from 'L' to 'H' and 'H' to 'L', resulting in prolonged time periods in incorrect states.
Innovation Solution
The semiconductor memory device incorporates a signal propagation circuit with a negative feedback circuit and a switch circuit configuration that includes an odd number of cascade-connected inverted signal output circuits, enabling quick switching and reducing signal loss by discharging or charging at high speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional signal propagation circuit is used, then the device complexity is low, but signal loss occurs due to manufacturing errors and attenuation
Solution Approach 1:
The patent implements a negative feedback circuit that monitors the output signal and feeds it back to the input stage. This feedback mechanism compensates for signal attenuation and manufacturing variations by automatically adjusting the signal level, thereby improving signal propagation reliability without requiring excessive complexity in the forward path
Solution Approach 2:
The circuit performs preliminary signal conditioning and level restoration before the signal reaches subsequent stages. By proactively compensating for expected attenuation and distortion in advance, the circuit maintains signal integrity throughout propagation without requiring complex error correction later
2Speed
If the signal propagation circuit uses simple configuration, then the manufacturing precision requirement is low, but switching speed is prolonged due to signal attenuation
Solution Approach 1:
The negative feedback loop continuously monitors output signal transitions and adjusts the driving strength accordingly. This allows the circuit to achieve fast switching speeds by dynamically compensating for component variations, reducing the stringency of manufacturing precision requirements while maintaining high performance
Solution Approach 2:
The circuit employs dynamic biasing and variable gain stages that adapt their operation based on real-time signal conditions. This dynamic adjustment enables fast switching by optimizing the operating point for speed while tolerating broader component value variations from manufacturing
3Loss of time
If conventional inverted signal output circuits are used, then the device complexity is low, but the time period in incorrect states is prolonged
Solution Approach 1:
The feedback circuit detects when output signals fail to reach the correct logic state within expected time and applies corrective drive signals. This closed-loop control reduces the duration of incorrect states by actively monitoring and correcting transition failures, justifying the added circuit complexity
Solution Approach 2:
The circuit implements preliminary drive strengthening and threshold adjustment before transitions that are prone to failure. By preemptively counteracting conditions that lead to prolonged incorrect states, the circuit reduces time loss without requiring complex real-time intervention mechanisms
Data Source
AI summary
A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.